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r01ds0264eu0100 rev.1.00 page 1 of 95 feb 23, 2016 features arm cortex-m0+ core ? armv6-m architecture ? maximum operating frequency: 32 mhz ? debug and trace: dwt, bpu, coresight? mtb-m0+ ? coresight debug port: sw-dp memory ? up to 128-kb code flash memory ? 4-kb data flash memory (up to 100,000 erase/write cycles) ? up to 16-kb sram ? 128-bit unique id connectivity ? usb 2.0 full-speed module (usbfs) - on-chip transceiver with voltage regulator - compliant with usb battery charging specification 1.2 ? serial communications interface (sci) 3 - uart - simple iic - simple spi ? serial peripheral interface (spi) 2 ? i 2 c bus interface (iic) 2 ? can module (can) analog ? 14-bit a/d converter (adc14) ? 12-bit d/a converter (dac12) ? low-power analog comparator (acmplp) 2 ? temperature sensor (tsn) timers ? general pwm timer 32-bit (gpt32) ? general pwm timer 16-bit (gpt16) 6 ? asynchronous general-purpose timer (agt) 2 ? watchdog timer (wdt) safety ? sram parity error check ? flash area protection ? adc self-diagnosis function ? clock frequency accuracy measurement circuit (cac) ? cyclic redundancy check (crc) calculator ? data operation circuit (doc) ? port output enab le for gpt (poeg) ? independent watchdog timer (iwdt) ? gpio readback level detection ? register write protection ? main oscillator stop detection system and power management ? low-power modes ? realtime clock (rtc) ? event link controller (elc) ? data transfer controller (dtc) ? key interrupt function (kint) ? power-on reset ? low voltage detection with voltage settings security and encryption ? aes128/256 ? true random number generator (trng) human machine interface (hmi) ? capacitive touch sensing unit (ctsu) multiple clock sources ? main clock oscillator (mosc) (1 to 20 mhz when vcc = 2.4 to 5.5 v) (1 to 8 mhz when vcc = 1.8 to 5.5 v) (1 to 4 mhz when vcc = 1.6 to 5.5 v) ? sub-clock oscillator (sosc) (32.768 khz) ? high-speed on-chip oscillator (hoco) (24, 32, 48, 64 mhz when vcc = 2.4 to 5.5 v) (24, 32, 48 mhz when vcc = 1.8 to 5.5 v) (24, 32 mhz when vcc = 1.6 to 5.5 v) ? middle-speed on-chip oscillator (moco) (8 mhz) ? low-speed on-chip oscillator (loco) (32.768 khz) ? independent watchdog timer oco (15 khz) ? clock trim function for hoco/moco/loco ? clock out support general purpose i/o ports ? up to 51 input/output pins - up to 3 cmos input - up to 48 cmos input/output - up to 6 5-v tolerant input/output (when vcc = 3.6 v) - up to 16 pins high current (20 ma) operating voltage ? vcc: 1.6 to 5.5 v operating temperature and packages ? ta = ?40c to +85c - 36-pin lga (4 mm 4 mm, 0.5 mm pitch) ? ta = ?40c to +105c - 64-pin lqfp (10 mm 10 mm, 0.5 mm pitch) - 48-pin lqfp (7 mm 7 mm, 0.5 mm pitch) - 64-pin qfn (8 mm 8 mm, 0.4 mm pitch) - 48-pin qfn (7 mm 7 mm, 0.5 mm pitch) - 40-pin qfn (6 mm 6 mm, 0.5 mm pitch) ultra-low power 32-mhz arm ? cortex ? -m0+ microcontroller, up to 128-kb code flash memory, 16-kb sram, capacitive touch sensing unit, 14-bit a/d converter, 12-bit d/a converter, security and safety features. features s124 mcu (ultra-low-power mcu) 32-bit arm ? cortex ? -m0+ microcontroller features
r01ds0264eu0100 rev.1.00 page 2 of 95 feb 23, 2016 s124 1. overview 1. overview the s124 mcu comprises multiple series of software- a nd pin-compatible arm-based 32-bit mcus that share a common set of renesas peripherals to facilitate design scal ability and efficient platform -based product development. based on the energy-efficient arm ? cortex ? -m0+ 32-bit core, this mcu is particul arly well suited for cost-sensitive and low-power applications. the mcu in this series feature: ? up to 128 kb code flash memory ? 16-kb sram ? capacitive touch sensing unit (ctsu) ? 14-bit adc ? 12-bit dac ? security features. 1.1 function outline table 1.1 arm core feature functional description arm cortex-m0+ ? maximum operating frequency: up to 32 mhz ? arm cortex-m0+: - revision: r0p1-00rel0 - armv6-m architecture profile - single-cycle integer multiplier. ? systick timer - driven by loco clock. table 1.2 memory feature functional description code flash memory maximum 128 kb code flash memory. see section 37, flash memory in user's manual. data flash memory 4 kb data flash memory. see section 37, flash memory in user's manual. option-setting memory the option-setting memory determines t he state of the mcu after a reset. see section 6, option-setting memory and information memory in user's manual. sram the mcu has an on-chip high-speed sram with even parity bit. see section 36, sram in user's manual. table 1.3 system (1/2) feature functional description operating mode two operating modes: ? single-chip mode ? sci boot mode. see section 3, operating modes in user's manual. reset the mcu has 9 types of resets: ? res pin reset ? power-on reset ? independent watchdog timer reset ? watchdog timer reset ? voltage monitor 0 reset ? voltage monitor 1 reset ? voltage monitor 2 reset ? sram parity error reset ? software reset. see section 5, resets in user's manual.
r01ds0264eu0100 rev.1.00 page 3 of 95 feb 23, 2016 s124 1. overview low voltage detection (lvd) the low voltage detection (lvd) monitors the voltage level input to the vcc pin and the detection level can be selected using a software program. see section 7, low voltage detection (lvd) in user's manual. clock ? main clock oscillator (mosc) ? sub-clock oscillator (sosc) ? high-speed on-chip oscillator (hoco) ? middle-speed on-chip oscillator (moco) ? low-speed on-chip oscillator (loco) ? independent watchdog timer on-chip oscillator ? clock out support. see section 8, clock generati on circuit in user's manual. clock frequency accuracy measurement circuit (cac) the clock frequency accuracy me asurement circuit (cac) is us ed to check the system clock frequency with a reference clock signal by coun ting the number of pulse s of the system clock to be measured. the reference clock can be provided externally through a cacref pin or internally from various on-chip oscillators. event signals can be generated when the cloc k does not match or measurement ends. this feature is particularly useful in im plementing a fail-safe mechanism for home and industrial automation applications. see section 9, clock frequenc y accuracy measurement circ uit (cac) in user's manual. low power mode the mcu has several functions for r educing power consumption, such as setting clock dividers, stopping modules, selecting power control mode in normal operation, and transitioning to low power modes. see sectio n 10, low power modes in user's manual. register write protection the register write protection func tion protects important registers from being overwritten due to software errors. see section 11, register write protection in user's manual. watchdog timer (wdt) the watchdog timer (wdt) is a 14-bi t down-counter. it can be used to reset the mcu when the counter underflows because the system has r un out of control and is unable to refresh the wdt. in addition, a non-maskable interrupt or interrupt can be generated by an underflow. the refresh-permitted period can be set to refresh the counter and used as the condition to detect when the system runs out of control. see sect ion 22, watchdog timer (wdt) in user's manual. independent watchdog timer (iwdt) the independent watchdog timer (iwdt) consists of a 14-bit down-counter that must be serviced periodically to prevent counter underflow. the iwdt provides functionality to reset the mcu or to generate a non-maskable interr upt/interrupt for a timer underflow. because the timer operates with an independent, dedica ted clock source, it is particularly useful in returning the mcu to a known state as a fail safe mechanism when the system runs out of control. the watchdog timer can be triggered automatically on reset, underflow, or refresh error, or by a refresh of the count value in the registers. see section 23, independent watchdog timer (iwdt) in user's manual. table 1.4 interrupt control feature functional description interrupt controller unit (icu) the interrupt controller unit (icu) controls which event signal s are linked to the nvic/dtc module. the icu also controls nmi interrupts. see section 12, interrupt controller unit (icu) in user's manual. table 1.5 event link feature functional description event link controller (elc) the event link controller (elc) uses the interrupt requests generated by various peripheral modules as event signals to connect them to different modules, enabling direct interaction between the modules without cpu intervention. see section 15, event link controller (elc) in user's manual. table 1.6 direct memory access feature functional description data transfer controller (dtc) the mcu incorporates a data transfer controller (dtc) that performs data transfers when activated by an interrupt request. see section 14, data transfer controller (dtc) in user's manual. table 1.3 system (2/2) feature functional description
r01ds0264eu0100 rev.1.00 page 4 of 95 feb 23, 2016 s124 1. overview table 1.7 timers feature functional description general pwm timer (gpt) the general pwm timer (gpt) is a 32-bit timer with 1 channel and a 16-bit timer with 6 channels. pwm waveforms can be generated by controlling the up-counter, down-counter, or the up- and down-counter. in addition, pwm wave forms for controlling brushless dc motors can be generated. the gpt can also be used as a general-purpose timer. see section 19, general pwm timer (gpt) in user's manual. port output enable for gpt (poeg) use the port output enable for gpt (poeg) function to plac e the general pwm timer (gpt) output pins in the output disable state. see section 18, port output enable for gpt (poeg) in user?s manual. asynchronous general purpose timer (agt) the asynchronous general purpose timer (agt) is a 16-bit timer that can be used for pulse output, external pulse width or period measurement, and counting external events. this 16-bit timer consists of a reload regist er and a down-counter. the reload register and the down-counter are allocated to the same addr ess, and they can be ac cessed with the agt register. see section 20, asynchronous gener al purpose timer (agt) in user's manual. realtime clock (rtc) the realtime clock (rtc) has two counting modes, calendar count mode and binary count mode, that are used by switching register settings. for calendar count mode, the rtc has a 100-year calendar from 2000 to 2099 and automatically adjusts dates for leap years. for binary count mode, the rtc counts seconds and retains the information as a serial value. binary count mode can be used for calendars ot her than the gregorian (western) calendar. see section 21, realtime cl ock (rtc) in user's manual. table 1.8 communication interfaces (1/2) feature functional description serial communications interface (sci) the serial communication interface (sci) is configurable to five asynchronous and synchronous serial interfaces: ? asynchronous interfaces (uart and asynch ronous communications interface adapter (acia)) ? 8-bit clock synchronous interface ? simple iic (master-only) ? simple spi ? smart card interface the smart card interface complies with the iso/iec 7816-3 standard for electronic signals and transmission protocol. sci0 has fifo buffers to enable continuous and full-duplex communication, and the data transfer speed can be configured independently using an on-chip baud rate generator. see section 25, serial communications interface (sci) in user's manual. i 2 c bus interface (iic) the mcu has a two-channel i 2 c bus interface (iic). the iic module conforms with and pr ovides a subset of the nxp i 2 c bus (inter-integrated circuit bus) interface functions. see section 26, i 2 c bus interface (iic) in user's manual. serial peripheral interface (spi) the mcu includes two independent channels of the serial peripheral interface (spi). the spi channels are capable of high-speed, full-dupl ex synchronous serial communications with multiple processors and peripheral devices. see se ction 28, serial peripheral interface (spi) in user's manual. controller area network (can) module the controller area network (can) module provi des functionality to receive and transmit data using a message-based protocol between multiple slaves and masters in electromagnetically noisy applications. the can module complies with the iso 11898-1 (can 2.0a/can 2.0b) standard and supports up to 32 mailboxes, which can be configured for transmission or reception in normal mailbox and fifo modes. both standard (11-bit) and extended (29-bit) messaging formats are supported. see section 27, controller ar ea network (can) module in user's manual.
r01ds0264eu0100 rev.1.00 page 5 of 95 feb 23, 2016 s124 1. overview usb 2.0 full-speed module (usbfs) the mcu incorporates a usb 2.0 full-speed module (usbfs). the usbfs is a usb controller that is equipped to operate as a device controller. the mo dule supports full-speed and low-speed transfer as defined in the universa l serial bus specification 2.0. the module has an internal usb transceiver and supports all of the transfer types defined in the universal serial bus specification 2.0. the usb has buffer memory for data transfer , providing a maximum of 5 pipes. pipe0 and pipe4 to pipe7 can be assigned any endpoint number based on the peripheral devices used for communication or based on the user system. the mcu supports revision 1.2 of the battery c harging specification. because the mcu can be powered at 5 v, the usb ldo regulator provides the internal usb transceiver power supply 3.3 v. see section 24, usb 2.0 full-speed module (usbfs) in user's manual. table 1.9 analog feature functional description 14-bit a/d converter (adc14) the mcu incorporates up to one uni t of a 14-bit successive approximation a/d converter. up to 18 analog input channels are selectable. temperature sensor output and internal reference voltage are selectable for conversion. the a/d conversion accuracy is selectable from 12-bit and 14-bit conversion making it possible to opt imize the tradeoff between speed and resolution in generating a digital value. see section 30, 14-bit a/d converter (adc14) in user's manual. 12-bit d/a converter (dac12) the mcu includes a 12-bit d/a conv erter with an output amplifier. see section 31, 12-bit d/a converter (dac12) in user's manual. temperature sensor (tsn) the on-chip temperature sensor can be used to determine and monitor the die temperature for reliable operation of the device. the sensor ou tputs a voltage directly proportional to the die temperature, and the relationship between the die temperature and the output voltage is linear. the output voltage is provided to the adc for conversion and can be further used by the end application. see section 32, temperatur e sensor (tsn) in user's manual. low-power analog comparator (acmplp) analog comparators can be used to compare a reference input voltage and analog input voltage. the comparison result can be read by software and also be output externally. the reference input voltage can be selected from either an input to the cmprefi (i = 0, 1) pin or from the internal reference voltage (vref) generated internally in this mcu. the acmplp response speed can be set befor e starting an operation. setting high-speed mode decreases the response delay time, but increases current consumption. setting low- speed mode increases the response delay time , but decreases current consumption. see section 33, low-power analog compar ator (acmplp) in user's manual. table 1.10 human machine interfaces feature functional description key interrupt function (kint) a key interrupt can be generated by setting the key return mode register (krm) and inputting a rising/falling edge to the key interrupt input pins. see section 17, key interrupt function (kint) in user's manual. capacitive touch sensing unit (ctsu) the capacitive touch sensing unit (ctsu) me asures the electrostatic capacitance of the touch sensor. changes in the electrostatic ca pacitance are determined by software, which enables the ctsu to detect whether a finger is in contact with the touch sensor. the electrode surface of the touch sensor is usually enclosed with an electrical conductor so that a finger does not come into direct contact with the electrode. see section 34, capacitive touch sensing unit (ctsu) in user's manual. table 1.11 data processing feature functional description cyclic redundancy check (crc) calculator the cyclic redundancy check (crc) generates crc codes to detect errors in the data. the bit order of crc calculation results can be swit ched for lsb first or msb first communication. additionally, various crc generat ion polynomials are availabl e. the snoop function allows monitoring reads from and writes to specific addresses. this func tion is useful in applications that require crc code to be generated automatically in certain events, such as monitoring writes to the serial transmit buffer and reads fr om the serial receive buffer. see section 29, cyclic redundancy check (crc) ca lculator in user's manual. table 1.8 communication interfaces (2/2) feature functional description
r01ds0264eu0100 rev.1.00 page 6 of 95 feb 23, 2016 s124 1. overview data operation circuit (doc) the data o peration circuit (doc) is used to comp are, add, and subtract 16-bit data. see section 35, data operation ci rcuit (doc) in user's manual. table 1.12 security feature functional description aes see the aes engine chapter. true random number generator (trng) see true random number generator chapter. table 1.11 data processing feature functional description
r01ds0264eu0100 rev.1.00 page 7 of 95 feb 23, 2016 s124 1. overview 1.2 block diagram figure 1.1 shows the block diagram of this mcu superset. individu al devices within the group may have a subset of the features. figure 1.1 block diagram memories 128 kb code flash 4 kb data flash 16 kb sram dma system icu interrupt control mode control power control register write protection mosc/sosc clocks (h/m/l) oco gpt32 1 gpt16 6 timers agt 2 rtc ctsu kint arm cortex-m0+ nvic system timer test and dbg i/f dtc wdt/iwdt cac por/lvd reset human machine interfaces elc event link aes + trng security analogs crc data processing doc communication interfaces iic 2 spi 2 can 1 usbfs with bc1.2 sci 3 tsn dac12 acmplp 2 adc14
r01ds0264eu0100 rev.1.00 page 8 of 95 feb 23, 2016 s124 1. overview 1.3 part numbering figure 1.2 part numbering scheme 7 3 a 0 1 c f m package type fm: lqfp 64 pins fl: lqfp 48 pins lm: lga 36 pins nb: qfn 64 pins ne: qfn 48 pins nf: qfn 40 pins quality id software id operating temperature 2: -40 c to 85 c 3: -40 c to 105 c code flash memory size 6: 64 kb 7: 128 kb feature set 7: superset group name 4: s124 core 2: arm cortex-m0+ series name 1: ultra low power renesas synergy family flash memory renesas microcontroller renesas r 7 f s 1 2 4 7
r01ds0264eu0100 rev.1.00 page 9 of 95 feb 23, 2016 s124 1. overview 1.4 function comparison table 1.13 function comparison parts number R7FS124773A01CFM/ r7fs124763a01cfm/ r7fs124773a01cnb/ r7fs124763a01cnb r7fs124773a01cfl/ r7fs124763a01cfl/ r7fs124773a01cne/ r7fs124763a01cne r7fs124773a01cnf/ r7fs124763a01cnf r7fs124772a01clm/ r7fs124762a01clm pin count 64 48 40 36 package lqfp/qfn lqfp/qfn qfn lga code flash memory 128/64 kb data flash memory 4 kb sram 16 kb parity 4 kb system cpu clock 32 mhz interrupt control icu yes event control elc 8 8 7 6 dma dtc yes timers gpt32 1 gpt166 644 agt2 222 rtc yes wdt/iwdt yes communication sci 3 iic 2 spi 2 can yes usbfs yes analog adc14 18 14 12 11 dac12 1 acmplp 2 tsn yes hmictsu31 231713 kint8 554 data processing crc yes doc yes security aes and trng
r01ds0264eu0100 rev.1.00 page 10 of 95 feb 23, 2016 s124 1. overview 1.5 pin functions table 1.14 pin functions (1/3) function signal i/o description power supply vcc input power supply pin. connect it to the system power supply. connect this pin to vss by a 0.1- f capacitor. the capacitor should be placed close to the pin. vcl input connect this pin to the vss pin by the smoothing capacitor used to stabilize the internal power supply. place the capacitor close to the pin. vss input ground pin. connect it to the system power supply (0 v). clock xtal output pins for a crystal resonator. an external clock signal can be input through the extal pin. extal input xcin input input/output pins for the sub-clo ck oscillator. connect a crystal resonator between xcout and xcin. xcout output clkout output clock output pin. operating mode control md input pins for setting the oper ating mode. the signal levels on these pins must not be changed during operation mode transiti on at the time of release from the reset state. system control res input reset signal input pin. the mcu enters the reset state when this signal goes low. cac cacref input measurement reference clock input pin. on-chip debug swdio i/o serial wire debug data input/output pin. swclk input serial wire clock pin. interrupt nmi input non-maskable interrupt request pin. irq0 to irq7 input maskable interrupt request pins. gpt gtetrga, gtetrgb input external trigger input pin. gtioc0a to gtioc6a, gtioc0b to gtioc6b i/o input capture, output compare, or pwm output pin. gtiu input hall sensor input pin u. gtiv input hall sensor input pin v. gtiw input hall sensor input pin w. gtouup output three-phase pwm output for bldc motor control (positive u phase). gtoulo output three-phase pwm output for bldc motor control (negative u phase). gtovup output three-phase pwm output for bldc motor control (positive v phase). gtovlo output three-phase pwm output for bldc motor control (negative v phase). gtowup output three-phase pwm output for bldc motor control (positive w phase). gtowlo output three-phase pwm output for bldc motor control (negative w phase). agt agtee0, agtee1 input external event input enable. agtio0, agtio1 i/o external event input and pulse output. agto0, agto1 output pulse output. agtoa0, agtoa1 output output compare match a output. agtob0, agtob1 output output compare match b output. rtc rtcout output output pin for 1-hz/64-hz clock.
r01ds0264eu0100 rev.1.00 page 11 of 95 feb 23, 2016 s124 1. overview sci sck0, sck1, sck9 i/o input/output pins for the cl ock (clock synchronous mode). rxd0, rxd1, rxd9 input input pins for received data (a synchronous mode/clock synchronous mode). txd0, txd1, txd9 output output pins for transmitted dat a (asynchronous mode/clock synchronous mode). cts0_rts0, cts1_rts1, cts9_rts9 i/o input/output pins for controlling t he start of transmission and reception (asynchronous mode/clock sync hronous mode), active low. scl0, scl1, scl9 i/o input/output pins for the iic clock (simple iic). sda0, sda1, sda9 i/o input/output pins for the iic data (simple iic). sck0, sck1, sck9 i/o input/output pins for the clock (simple spi). miso0, miso1, miso9 i/o input/output pins for slave tr ansmission of data (simple spi). mosi0, mosi1, mosi9 i/o input/output pins for master transmission of data (simple spi). ss0, ss1, ss9 input slave-select input pins (simple spi), active low. iic scl0, scl1 i/o input/output pins for clock. sda0, sda1 i/o input/output pins for data. spi rspcka, rspckb i/o clock input/output pin. mosia, mosib i/o inputs or outputs data output from the master. misoa, misob i/o inputs or outputs data output from the slave. ssla0, sslb0 i/o input or output pin for slave selection. ssla1 to ssla3, sslb1 to sslb3 output output pin for slave selection. can crx0 input receive data. ctx0 output transmit data. usbfs vss_usb input ground pins. vcc_usb_ldo input power supply pin for usb ldo regulator. vcc_usb i/o input: power supply pin for usb transceiver. output: usb ldo regulator output pin. this pin should be connected to an external capacitor. usb_dp i/o d+ i/o pin of the usb on-chip tr ansceiver. this pin should be connected to the d+ pin of the usb bus. usb_dm i/o d? i/o pin of the usb on-chip tr ansceiver. this pin s hould be connected to the d? pin of the usb bus. usb_vbus input usb cable connection monitor pin. this pin should be connected to vbus of the usb bus. the vbus pin status (connected or disconnected) can be detected when the usb module is oper ating as a function controller. analog power supply avcc0 input analog voltage supply pin for the analog. connect this pin to vcc. avss0 input analog ground pin. connect this pin to vss. vrefh0 input analog reference voltage supply pi n for the a/d converter. connect this pin to vcc when not using the a/d converter. vrefl0 input analog reference ground pin for the a/d converter. connect this pin to vss when not using the a/d converter. table 1.14 pin functions (2/3) function signal i/o description
r01ds0264eu0100 rev.1.00 page 12 of 95 feb 23, 2016 s124 1. overview adc14 an000 to an010, an016 to an022 input input pins for the analog signals to be processed by the a/d converter. adtrg0 input input pins for the external trig ger signals that start the a/d conversion, active low. dac12 da0 output output pins for the analog sign als to be processed by the d/a converter. acmplp vcout output comparator output pin. cmpref0, cmpref1 input reference voltage input pins. cmpin0, cmpin1 input analog voltage input pins. ctsu ts00 to ts28, ts30, ts31 input capacitive touch det ection pins (touch pins). tscap - secondary power supply pin for the touch driver. kint kr00 to kr07 input key interrupt input pins. i/o ports p000 to p004, p010 to p015 i/o general-purpose input/output pins. p100 to p113 i/o general-purpose input/output pins. p200 input general-purpose input pin. p201, p204 to p206, p212, p213 i/o general-purpose input/output pins. p214, p215 input general-purpose input pins. p300 to p304 i/o general-purpose input/output pins. p400 to p403, p407 to p411 i/o general-purpose input/output pins. p500 to p502 i/o general-purpose input/output pins. table 1.14 pin functions (3/3) function signal i/o description
r01ds0264eu0100 rev.1.00 page 13 of 95 feb 23, 2016 s124 1. overview 1.6 pin assignments figure 1.3 to figure 1.8 show the pin assignments. figure 1.3 pin assignment for lqfp 64-pin (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 p501 p502 p015 p014 p012 avcc0 avss0 p011/vrefl0 p010/vrefh0 p004 p003 p002 p001 p013 p300/swclk p301 p302 p303 p304 p201/md res p204 p205 p206 vcc_usb_ldo vcc_usb usb_dp usb_dm vss_usb p200 p100 p102 p103 p104 p105 p106 p107 vss vcc p113 p112 p111 p110 p108/swdio p101 p109 p400 p402 p403 vcl p215/xcin p214/xcout vss p213/xtal p212/extal vcc p411 p410 p408 p407 p401 p409 p000 r7fs1247x3a01cfm p500
r01ds0264eu0100 rev.1.00 page 14 of 95 feb 23, 2016 s124 1. overview figure 1.4 pin assignment for qfn 64-pin (top view) p300/swclk p301 p302 p303 p304 p201/md res p204 p205 p206 vcc_usb_ldo vcc_usb usb_dp usb_dm vss_usb p200 p100 p102 p103 p104 p105 p106 p107 vss vcc p113 p112 p111 p110 p108/swdio p101 p109 p400 p402 p403 vcl p215/xcin p214/xcout vss p213/xtal p212/extal vcc p411 p410 p408 p407 p401 p409 r7fs1247x3a01cnb 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 p500 p501 p502 p015 p014 p012 avcc0 avss0 p011/vrefl0 p010/vrefh0 p004 p003 p002 p001 p000 p013
r01ds0264eu0100 rev.1.00 page 15 of 95 feb 23, 2016 s124 1. overview figure 1.5 pin assignment for lqfp 48-pin (top view) figure 1.6 pin assignment for qfn 48-pin (top view) 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 37 38 39 40 41 42 43 44 45 46 47 48 p500 p014 p013 p012 avcc0 avss0 p011/vrefl0 p010/vrefh0 p002 p001 p015 p300/swclk p302 p200 p201/md res p206 vcc_usb_ldo vcc_usb usb_dp usb_dm vss_usb p301 p100 p101 p102 p103 p104 vss vcc p112 p111 p110 p108/swdio p109 p400 vcl p215/xcin p214/xcout vss p213/xtal p212/extal vcc p408 p407 p401 p409 p000 r7fs1247x3a01cfl p300/swclk p302 p200 p201/md res p206 vcc_usb_ldo vcc_usb usb_dp usb_dm vss_usb p301 p100 p102 p103 p104 vss vcc p112 p111 p110 p109 p108/swdio p101 p400 vcl p215/xcin p214/xcout vss p213/xtal p212/extal vcc p409 p408 p407 p401 r7fs1247x3a01cne 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 12 11 10 9 8 7 6 5 4 3 2 1 48 47 46 45 44 43 42 41 40 39 38 37 p500 p014 p013 p012 avcc0 avss0 p011/vrefl0 p010/vrefh0 p002 p001 p000 p015
r01ds0264eu0100 rev.1.00 page 16 of 95 feb 23, 2016 s124 1. overview figure 1.7 pin assignment for qfn 40-pin (top view) figure 1.8 pin assignment for lga 36-pin (top view, pad side down) p300/swclk p301 p200 p201/md res vcc_usb_ldo vcc_usb usb_dp usb_dm vss_usb p100 p102 p103 p104 p112 p111 p110 p109 p108/swdio p101 p400 p215/xcin p214/xcout vss p213/xtal p212/extal vcc p408 p407 vcl r7fs1247x3a01cnf 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 10 9 8 7 6 5 4 3 2 1 40 39 38 37 36 35 34 33 32 31 p015 p014 p013 p012 avcc0 avss0 p011/vrefl0 p010/vrefh0 p001 p000 avss0 avcc0 p014 p015 p011 /vrefl0 p012 p013 p100 p214 /xcout p400 p103 p102 p101 p112 vss p212 /extal p213 /xtal p109 p110 p111 vcc p407 res p201/md p200 p108 /swdio vss_usb usb_dm usb_dp vcc_usb vcc_usb _ldo p300 /swclk p000 p215 /xcin vcl p010 /vrefh0 r7fs1247x2a01clm 6 5 4 3 2 1 6 5 4 3 2 1 d e f a b c d e f a b c
r01ds0264eu0100 rev.1.00 page 17 of 95 feb 23, 2016 s124 1. overview 1.7 pin lists pin number power, system, clock, debug, cac i/o ports timers communication interfaces analogs hmi lqfp64 lqfp48 qfn48 qfn40 lga36 agt gpt_ops, poeg gpt rtc usbfs,can sci iic spi adc14 dac12, acmplp ctsu interrupt 1111c2cacref_ c p400 agtio1_ d gtioc6a _a sck0_b/ sck1_b scl0_a ts20 irq0 222 - - p401 gtetrg a_b gtioc6b _a ctx0_b cts0_rt s0_b/ ss0_b/ txd1_b/ mosi1_b/ sda1_b sda0_a ts19 irq5 3 - - - - p402 crx0_b rxd1_b/ miso1_b/ scl1_b ts18 irq4 4---- p403 gtioc3a _b cts1_rt s1_b/ ss1_b ts17 5332a1vcl 6443b1xcinp215 7 5 5 4 c1 xcout p214 8665d1vss 9776d3xtalp213 gtetrg a_d txd1_a/ mosi1_a/ sda1_a irq2 10 8 8 7 d2 extal p212 agtee1 gtetrg b_d rxd1_a/ miso1_a/ scl1_a irq3 11 9 9 8 e1 vcc 12 - - - - p411 agtoa1 gtovup _b gtioc6a _b txd0_b/ mosi0_b/ sda0_b mosia_b ts07 irq4 13 - - - - p410 agtob1 gtovlo _b gtioc6b _b rxd0_b/ miso0_b/ scl0_b misoa_b ts06 irq5 14 10 10 - - p409 gtowup _b gtioc5a _b txd9_a/ mosi9_a/ sda9_a ts05 irq6 15 11 11 9 - p408 gtowlo _b gtioc5b _b rxd9_a/ miso9_a/ scl9_a ts04 irq7 16 12 12 10 e2 p407 rtcout usb_vbu s cts0_rt s0_d/ ss0_d sda0_b sslb3_a adtrg0_ b ts03 17 13 13 11 f1 vss_usb 18 14 14 12 f2 usb_dm 19 15 15 13 f3 usb_dp 20 16 16 14 f4 vcc_us b 21 17 17 15 f5 vcc_us b_ldo 22 18 18 - - p206 gtiu_a rxd0_d/ miso0_d/ scl0_d sda1_a sslb1_a ts01 irq0 23 - - - - clkout_ a p205 agto1 gtiv_a gtioc4a _b txd0_d/ mosi0_d/ sda0_d/ cts9_rt s9_a/ ss9_a scl1_a sslb0_a tscap_a irq1 24----cacref_ a p204 agtio1_ a gtiw_a gtioc4b _b sck0_d/ sck9_a scl0_b rspckb_ a ts00 25 19 19 16 e3 res 26 20 20 17 e4 md p201 27 21 21 18 e5 p200 nmi 28 - - - - p304 gtioc1a _b 29 - - - - p303 gtioc1b _b ts02 30 22 22 - - p302 gtouup _a gtioc4a _a sslb3_b ts08 irq5 31 23 23 19 - p301 gtoulo _a gtioc4b _a sslb2_b ts09 irq6 32 24 24 20 f6 swclk p300 gtouup _c gtioc0a _a sslb1_b 33 25 25 21 e6 swdio p108 gtoulo _c gtioc0b _a cts9_rt s9_b/ ss9_b sslb0_b 34 26 26 22 d4 clkout_ b p109 gtovup _a gtioc1a _a ctx0_a txd9_b/ mosi9_b/ sda9_b mosib_b ts10
r01ds0264eu0100 rev.1.00 page 18 of 95 feb 23, 2016 s124 1. overview note: several pin names have the added suffix of _a, _b, _c, and _d. the suffix can be ignored when assigning functionality. 35 27 27 23 d5 p110 gtovlo _a gtioc1b _a crx0_a cts0_rt s0_c/ ss0_c/ rxd9_b/ miso9_b/ scl9_b misob_b vcout ts11 irq3 36 28 28 24 d6 p111 gtioc3a _a sck0_c/ sck9_b rspckb_ b ts12 irq4 37 29 29 25 c6 p112 gtioc3b _a txd0_c/ mosi0_c/ sda0_c tscap_c 38---- p113 39 30 30 - - vcc 40 31 31 - - vss 41 - - - - p107 gtioc0a _b kr07 42 - - - - p106 gtioc0b _b ssla3_a kr06 43 - - - - p105 gtetrg a_c ssla2_a kr05/ irq0 44 32 32 26 - p104 gtetrg b_b rxd0_c/ miso0_c/ scl0_c ssla1_a ts13 kr04/ irq1 45 33 33 27 c3 p103 gtowup _a gtioc2a _a ctx0_c cts0_rt s0_a/ ss0_a ssla0_a an019 cmpref 1 ts14 kr03 46 34 34 28 c4 p102 agto0 gtowlo _a gtioc2b _a crx0_c sck0_a rspcka_ a an020/ adtrg0_ a cmpin1 ts15 kr02 47 35 35 29 c5 p101 agtee0 gtetrg b_a gtioc5a _a txd0_a/ mosi0_a/ sda0_a/ cts1_rt s1_a/ ss1_a sda1_b mosia_a an021 cmpref 0 ts16 kr01/ irq1 48 36 36 30 b6 p100 agtio0_ a gtetrg a_a gtioc5b _a rxd0_a/ miso0_a/ scl0_a/ sck1_a scl1_b misoa_a an022 cmpin0 ts26 kr00/ irq2 49 37 37 - - p500 agtoa0 gtiu_b gtioc2a _b an016 ts27 50 - - - - p501 agtob0 gtiv_b gtioc2b _b an017 51 - - - - p502 gtiw_b gtioc3b _b an018 52 38 38 31 a6 p015 an010 ts28 irq7 53 39 39 32 a5 p014 an009 da0 54 40 40 33 b5 p013 an008 55 41 41 34 b4 p012 an007 56 42 42 35 a4 avcc0 57 43 43 36 a3 avss0 58 44 44 37 b3 vrefl0 p011 an006 ts31 59 45 45 38 a2 vrefh0 p010 an005 ts30 60 - - - - p004 an004 ts25 irq3 61 - - - - p003 an003 ts24 62 46 46 - - p002 an002 ts23 irq2 63 47 47 39 - p001 an001 ts22 irq7 64 48 48 40 b2 p000 an000 ts21 irq6 pin number power, system, clock, debug, cac i/o ports timers communication interfaces analogs hmi lqfp64 lqfp48 qfn48 qfn40 lga36 agt gpt_ops, poeg gpt rtc usbfs,can sci iic spi adc14 dac12, acmplp ctsu interrupt
r01ds0264eu0100 rev.1.00 page 19 of 95 feb 23, 2016 s124 2. electrical characteristics 2. electrical characteristics unless otherwise specified, th e electrical characteristics of the mcu ar e defined under the following conditions: vcc * 1 = avcc0 = vcc_usb * 2 = vcc_usb_ldo * 2 = 1.6 to 5.5v, vrefh0 = 1.6 to avcc0, vss = avss0 = vrefl0 = vss_usb = 0 v, ta = t opr note 1. the typical condition is set to vcc = 3.3v. note 2. when usbfs is not used. figure 2.1 shows the timing conditions. figure 2.1 input or output timing measurement conditions the measurement conditions of timing specification in each peripherals are recommended for the best peripheral operation. however, make sure to adjust driving abilities of each pins to meet your conditions. for example p100 c v oh = vcc 0.7, v ol = vcc 0.3 v ih = vcc 0.7, v il = vcc 0.3 load capacitance c = 30pf
r01ds0264eu0100 rev.1.00 page 20 of 95 feb 23, 2016 s124 2. electrical characteristics 2.1 absolute maximum ratings caution: permanent damage to the mcu may result if absolute maximum ratings are exceeded. to preclude any malfunctions due to noise interference, insert capacitors of high frequency characteristics be tween the vcc and vss pins , between the avcc0 and avss0 pins, between the vcc_usb and vss_usb pins, and between the vrefh0 and vrefl0 pins. place capacitors of about 0.1 f as close as possible to every power supply pi n and use the shortest and heaviest possible traces. also, connect capacitors as stabilization capacitance. connect the vcl pin to a vss pin by a 4.7-f capa citor. the capacitor must be placed close to the pin. note 1. ports p205, p206, p400, p401, and p407 are 5v-tolerant. do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up might cause malfunction and the abnormal current that passes in the device at this time might cause degradation of internal elements. note 2. see section 2.2.1, tj/ta definition . note 3. contact renesas electronics sales office for information on derating operation under ta = +85c to +105c. derating is the systematic reduction of load for improved reliability. table 2.1 absolute maximum ratings item symbol value unit power supply voltage vcc ?0.5 to +6.5 v input voltage 5v-tolerant ports* 1 v in ?0.3 to +6.5 v p000 to p004 p010 to p015 v in ?0.3 to avcc0 + 0.3 v others v in ?0.3 to vcc + 0.3 v reference power supply voltage vrefh0 ?0.3 to +6.5 v analog power supply voltage avcc0 ?0.5 to +6.5 v usb power supply voltage vcc_usb ?0.5 to +6.5 v vcc_usb_ldo ?0.5 to +6.5 v analog input voltage when an000 to an010 are used v an ?0.3 to avcc0 + 0.3 v when an016 to an022 are used ?0.3 to vcc + 0.3 v operating temperature* 2 * 3 t opr ?40 to +105 c storage temperature t stg ?55 to +125 c
r01ds0264eu0100 rev.1.00 page 21 of 95 feb 23, 2016 s124 2. electrical characteristics note 1. use avcc0 and vcc under the following conditions: avcc0 and vcc can be set individually within the operating range when vcc 2.0 v avcc0 = vcc when vcc < 2.0 v. note 2. when powering on the vcc and avcc0 pins, power them on at the same time or the vcc pin first and then the avcc0 pin. table 2.2 recommended operating conditions item symbol value min typ max unit power supply voltages vcc *1, *2 when usbfs is not used 1.6 - 5.5 v when usbfs is used usb regulator disable vcc_usb - 3.6 v when usbfs is used usb regulator enable vcc_usb _ldo -5.5v vss -0-v usb power supply voltages vcc_usb when usbfs is not used -vcc-v when usbfs is used usb regulator disable (input) 3.0 3.3 3.6 v vcc_usb_ldo when usbfs is not used -vcc-v when usbfs is used usb regulator enable 3.8 - 5.5 v vss_usb - 0 - v analog power supply voltages avcc0 *1, *2 1.6 - 5.5 v avss0 - 0 - v vrefh0 when used as adc14 reference 1.6 - avcc0 v vrefl0 - 0 - v
r01ds0264eu0100 rev.1.00 page 22 of 95 feb 23, 2016 s124 2. electrical characteristics 2.2 dc characteristics 2.2.1 tj/ta definition note: make sure that tj = t a + ja total power consumption (w), where total power consumption = (vcc ? v oh ) i oh + v ol i ol + i cc max vcc. 2.2.2 i/o v ih , v il note 1. scl0_a, sda0_a, sda0_b, scl1_a, sda1_a (total 5 pins) note 2. scl0_a, sda0_a, scl0_b, sda0_b, scl1_ a, sda1_a, scl1_b, sda1_b (total 8 pins) note 3. p205, p206, p400, p401, p407 (total 5pins) table 2.3 dc characteristics conditions: products with operating temperature (t a ) ?40 to +105c item symbol typ max unit test conditions permissible junction temperature tj - 125 c high-speed mode middle-speed mode low-voltage mode low-speed mode subosc-speed mode table 2.4 i/o v ih , v il (1) conditions: vcc = avcc0 = 2.7 to 5.5 v item symbol min typ max unit test conditions schmitt trigger input voltage iic (except for smbus)* 1 v ih vcc 0.7 - 5.8 v - v il ?0.3 - vcc 0.3 ? v t vcc 0.05 - - res, nmi other peripheral input pins excluding iic v ih vcc 0.8 - vcc + 0.3 v il ?0.3 - vcc 0.2 ? v t vcc 0.1 - - input voltage (except for schmitt trigger input pin) iic (smbus)* 2 v ih 2.2 - vcc + 0.3 vcc = 3.6 to 5.5 v v ih 2.0 - vcc + 0.3 vcc =2.7 to 3.6 v v il ?0.3 - 0.8 - 5v-tolerant ports* 3 v ih vcc 0.8 - 5.8 v il ?0.3 - vcc 0.2 p000 to p004 p010 to p015 v ih avcc0 0.8 - avcc0 + 0.3 v il ?0.3 - avcc0 0.2 extal input ports pins except for p000 to p004, p010 to p015 v ih vcc 0.8 - vcc + 0.3 v il ?0.3 - vcc 0.2
r01ds0264eu0100 rev.1.00 page 23 of 95 feb 23, 2016 s124 2. electrical characteristics note 1. p205, p206, p400, p401, p407 (total 5pins) table 2.5 i/o v ih , v il (2) conditions: vcc = avcc0 = 1.6 to 2.7 v item symbol min typ max unit test conditions schmitt trigger input voltage res, nmi peripheral input pins v ih vcc 0.8 - vcc + 0.3 v - v il ?0.3 - vcc 0.2 ? v t vcc 0.01 - - input voltage (except for schmitt trigger input pin) 5v-tolerant ports* 1 v ih vcc 0.8 - 5.8 v il ?0.3 - vcc 0.2 p000 to p004 p010 to p015 v ih avcc0 0.8 - avcc0 + 0.3 v il ?0.3 - avcc0 0.2 extal input ports pins except for p000 to p004, p010 to p015 v ih vcc 0.8 - vcc + 0.3 v il ?0.3 - vcc 0.2
r01ds0264eu0100 rev.1.00 page 24 of 95 feb 23, 2016 s124 2. electrical characteristics 2.2.3 i/o i oh , i ol caution: to protect the reliability of the mcu, the outp ut current values should not exceed the values in this table. the average output current indicates the average value of current measured during 100 s. note 1. this is the value when low driving ability is select ed with the port drive capability bit in the pmnpfs register. note 2. this is the value when middle driving ability is sele cted with the port drive capability bit in the pmnpfs register. note 3. except for ports p200, p2 14, p215, which are input ports. table 2.6 i/o i oh , i ol conditions: vcc = avcc0 = 1.6 to 5.5 v item symbol min typ max unit permissible output current (average value per pin) ports p000 to p004, p010 to p015, p212, p213 - i oh --?4.0ma i ol --4.0ma ports p408, p409 low drive* 1 i oh --?4.0ma i ol --4.0ma middle drive* 2 vcc = 2.7 to 3.0 v i oh --?8.0ma i ol --8.0ma middle drive* 2 vcc = 3.0 to 5.5 v i oh --?20.0ma i ol --20.0ma other output pins* 3 low drive* 1 i oh --?4.0ma i ol --4.0ma middle drive* 2 i oh --?8.0ma i ol --8.0ma permissible output current (max value per pin) ports p000 to p004, p010 to p015, p212, p213 - i oh --?4.0ma i ol --4.0ma ports p408, p409 low drive* 1 i oh --?4.0ma i ol --4.0ma middle drive* 2 vcc = 2.7 to 3.0 v i oh --?8.0ma i ol --8.0ma middle drive* 2 vcc = 3.0 to 5.5 v i oh --?20.0ma i ol --20.0ma other output pins*3 low drive* 1 i oh --?4.0ma i ol --4.0ma middle drive* 2 i oh --?8.0ma i ol --8.0ma permissible output current (max value total pins) total of ports p000 to p004, p010 to p015 i oh (max) --?30ma i ol (max) --30ma total of all output pin i oh (max) --?60ma i ol (max) --60ma
r01ds0264eu0100 rev.1.00 page 25 of 95 feb 23, 2016 s124 2. electrical characteristics 2.2.4 i/o v oh , v ol , and other c haracteristics note 1. scl0_a, sda0_a, scl0_b, sda0_b, scl1_ a, sda1_a, scl1_b, sda1_b (total 8 pins). note 2. this is the value when middle driving ability is sele cted with the port drive capability bit in the pmnpfs register. note 3. based on characterization data, not tested in production. note 4. except for ports p200, p2 14, p215, which are input ports. note 1. scl0_a, sda0_a, scl0_b, sda0_b, scl1_ a, sda1_a, scl1_b, sda1_b (total 8 pins). note 2. this is the value when middle driving ability is sele cted with the port drive capability bit in the pmnpfs register. note 3. based on characterization data, not tested in production. note 4. except for ports p200, p2 14, p215, which are input ports. table 2.7 i/o v oh , v ol (1) conditions: vcc = avcc0 = 4.0 to 5.5 v item symbol min typ max unit test conditions output voltage iic* 1, * 2 v ol --0.4vi ol = 3.0 ma v ol --0.6 i ol = 6.0 ma ports p408, p409* 2, * 3 v oh vcc ? 1.0 - - i oh = ?20 ma v ol --1.0 i ol = 20 ma ports p000 to p004 p010 to p015 low drive v oh avcc0 ? 0.8 -i oh = ?2.0 ma v ol --0.8 i ol = 2.0 ma middle drive v oh avcc0 ? 0.8 -i oh = ?4.0 ma v ol --0.8 i ol = 4.0 ma other output pins* 4 low drive v oh vcc ? 0.8 - - i oh = ?2.0 ma v ol --0.8 i ol = 2.0 ma middle drive v oh vcc ? 0.8 - - i oh = ?4.0 ma v ol --0.8 i ol = 4.0 ma table 2.8 i/o v oh , v ol (2) conditions: vcc = avcc0 = 2.7 to 4.0 v item symbol min typ max unit test conditions output voltage iic* 1, * 2 v ol --0.4vi ol = 3.0 ma v ol --0.6 i ol = 6.0 ma ports p408, p409* 2, * 3 v oh vcc ? 1.0 - - i oh = ?20 ma vcc = 3.3 v v ol --1.0 i ol = 20 ma vcc = 3.3 v ports p000 to p004 p010 to p015 low drive v oh avcc0 ? 0.5 -- i oh = ?1.0 ma v ol --0.5 i ol = 1.0 ma middle drive v oh avcc0 ? 0.5 -- i oh = ?2.0 ma v ol --0.5 i ol = 2.0 ma other output pins* 4 low drive v oh vcc ? 0.5 - - i oh = ?1.0 ma v ol --0.5 i ol = 1.0 ma middle drive v oh vcc ? 0.5 - - i oh = ?2.0 ma v ol --0.5 i ol = 2.0 ma
r01ds0264eu0100 rev.1.00 page 26 of 95 feb 23, 2016 s124 2. electrical characteristics note 1. except for ports p200, p2 14, p215, which are input ports. table 2.9 i/o v oh , v ol (3) conditions: vcc = avcc0 = 1.6 to 2.7 v item symbol min typ max unit test conditions output voltage ports p000 to p004 p010 to p015 low drive v oh avcc0 ? 0.3 -- i oh = ?0.5 ma v ol --0.3 i ol = 0.5 ma middle drive v oh avcc0 ? 0.3 -- i oh = ?1.0 ma v ol --0.3 i ol = 1.0 ma other output pins* 1 low drive v oh vcc ? 0.3 - - v i oh = ?0.5 ma v ol --0.3 i ol = 0.5 ma middle drive v oh vcc ? 0.3 - - i oh = ?1.0 ma v ol --0.3 i ol = 1.0 ma table 2.10 i/o other characteristics conditions: vcc = avcc0 = 1.6 to 5.5 v item symbol min typ max unit test conditions input leakage current res, ports p200, p214, p215 | i in | - - 1.0 av in = 0 v v in = vcc three-state leakage current (off state) 5v-tolerant ports | i tsi | - - 1.0 av in = 0 v v in = 5.8 v other ports - - 1.0 v in = 0 v v in = vcc input pull-up resistor all ports (except for p200, p214, p215) r u 10 20 50 k ? v in = 0 v input capacitance usb_dp, usb_dm, p200 c in - - 30 pf v in = 0 v f = 1 mhz t a = 25c other input pins - - 15
r01ds0264eu0100 rev.1.00 page 27 of 95 feb 23, 2016 s124 2. electrical characteristics 2.2.5 i/o pin output characte ristics of low drive capacity figure 2.2 v oh /v ol and i oh /i ol voltage characteristics at ta = 25c when low drive output is selected (reference data) figure 2.3 v oh /v ol and i oh /i ol temperature characteristics at vcc = 1.6 v when low drive output is selected (reference data) 0123456 -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 i oh /i ol vs v oh /v ol v oh /v ol [v] i oh /i ol [ma] vcc = 5.5 v vcc = 3.3 v vcc = 2.7 v vcc = 1.6 v vcc = 1.6 v vcc = 2.7 v vcc = 3.3 v vcc = 5.5 v 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 -3 -2 -1 0 1 2 3 i oh /i ol vs v oh /v ol v oh /v ol [v] i oh /i ol [ma] ta = -40c ta = 105c ta = 25c ta = 105c ta = -40c ta = 25c
r01ds0264eu0100 rev.1.00 page 28 of 95 feb 23, 2016 s124 2. electrical characteristics figure 2.4 v oh /v ol and i oh /i ol temperature characteristics at vcc = 2.7 v when low drive output is selected (reference data) figure 2.5 v oh /v ol and i oh /i ol temperature characteristics at vcc = 3.3 v when low drive output is selected (reference data) 0 0.5 1 1.5 2 2.5 3 -20 -15 -10 -5 0 5 10 15 20 i oh /i ol vs v oh /v ol v oh /v ol [v] i oh /i ol [ma] ta = -40c ta = 105c ta = 25c ta = 105c ta = -40c ta = 25c 0 0.5 1 1.5 2 2.5 3 3.5 -30 -20 -10 0 10 20 30 i oh /i ol vs v oh /v ol v oh /v ol [v] i o h / i o l [ m a ] ta = -40c ta = 105c ta = 25c ta = 105c ta = -40c ta = 25c
r01ds0264eu0100 rev.1.00 page 29 of 95 feb 23, 2016 s124 2. electrical characteristics figure 2.6 v oh /v ol and i oh /i ol temperature characteristics at vcc = 5.5 v when low drive output is selected (reference data) 2.2.6 i/o pin output characteri stics of middle drive capacity figure 2.7 v oh /v ol and i oh /i ol voltage characteristics at ta = 25c when middle drive output is selected (reference data) 0123456 -60 -40 -20 0 20 40 60 i oh /i ol vs v oh /v ol v oh /v ol [v] i oh /i ol [ma] ta = -40c ta = 105c ta = 25c ta = 105c ta = -40c ta = 25c 0123456 -140 -120 -100 -80 -60 -40 -20 0 20 40 60 80 100 120 140 i oh /i ol vs v oh /v ol v oh /v ol [v] i oh /i ol [ma] vcc = 5.5 v vcc = 3.3 v vcc = 2.7 v vcc = 1.6 v vcc = 1.6 v vcc = 2.7 v vcc = 3.3 v vcc = 5.5 v
r01ds0264eu0100 rev.1.00 page 30 of 95 feb 23, 2016 s124 2. electrical characteristics figure 2.8 v oh /v ol and i oh /i ol temperature characteristics at vcc = 1.6 v when middle drive output is selected (reference data) figure 2.9 v oh /v ol and i oh /i ol temperature characteristics at vcc = 2.7 v when middle drive output is selected (reference data) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 -6 -4 -2 0 2 4 6 i oh /i ol vs v oh /v ol v oh /v ol [v] i oh /i ol [ma] ta = -40c ta = 105c ta = 25c ta = 105c ta = -40c ta = 25c 00.511.522.53 -40 -30 -20 -10 0 10 20 30 40 i oh /i ol vs v oh /v ol v oh /v ol [v] i oh /i ol [ma] ta = -40c ta = 105c ta = 25c ta = 105c ta = -40c ta = 25c
r01ds0264eu0100 rev.1.00 page 31 of 95 feb 23, 2016 s124 2. electrical characteristics figure 2.10 v oh /v ol and i oh /i ol temperature characteristics at vcc = 3.3 v when middle drive output is selected (reference data) figure 2.11 v oh /v ol and i oh /i ol temperature characteristics at vcc = 5.5 v when middle drive output is selected (reference data) 00.511.522.533.5 -60 -40 -20 0 20 40 60 i oh /i ol vs v oh /v ol v oh /v ol [v] i oh /i ol [ma] ta = -40c ta = 105c ta = 25c ta = 105c ta = -40c ta = 25c 0123456 -140 -120 -100 -80 -60 -40 -20 0 20 40 60 80 100 120 140 i oh /i ol vs v oh /v ol v oh /v ol [v] i oh /i ol [ma] ta = -40c ta = 105c ta = 25c ta = 105c ta = -40c ta = 25c
r01ds0264eu0100 rev.1.00 page 32 of 95 feb 23, 2016 s124 2. electrical characteristics 2.2.7 p408, p409 i/o pin ou tput characteristics of middle drive capacity figure 2.12 v oh /v ol and i oh /i ol voltage characteristics at ta = 25c when middle drive output is selected (reference data) figure 2.13 v oh /v ol and i oh /i ol temperature characteristics at vcc = 2.7 v when low drive output is selected (reference data) 0123456 i oh /i ol vs v oh /v ol v oh /v ol [v] i oh /i ol [ma] vcc = 5.5 v vcc = 3.3 v vcc = 2.7 v vcc = 2.7 v vcc = 3.3 v vcc = 5.5 v -140 -120 -100 -80 -60 -40 -20 20 40 60 80 100 120 140 200 180 160 0 -160 -180 -200 0 0.5 1 1.5 2 2.5 3 -60 -40 -20 0 20 40 60 i oh /i ol vs v oh /v ol v oh /v ol [v] i oh /i ol [ma] ta = -40c ta = 105c ta = 25c ta = 105c ta = -40c ta = 25c
r01ds0264eu0100 rev.1.00 page 33 of 95 feb 23, 2016 s124 2. electrical characteristics figure 2.14 v oh /v ol and i oh /i ol temperature characteristics at vcc = 3.3 v when middle drive output is selected (reference data) figure 2.15 v oh /v ol and i oh /i ol temperature characteristics at vcc = 5.5 v when low drive output is selected (reference data) 0 0.5 1 1.5 2 2.5 3 3.5 -100 -80 -60 -40 -20 0 20 40 60 80 100 i oh /i ol vs v oh /v ol v oh /v ol [v] i oh /i ol [ma] ta = -40c ta = 105c ta = 25c ta = 105c ta = -40c ta = 25c 0123456 -220 -180 -140 -100 -60 -20 20 60 100 140 180 220 i oh /i ol vs v oh /v ol v oh /v ol [v] i oh /i ol [ma] ta = -40c ta = 105c ta = 25c ta = 105c ta = -40c ta = 25c
r01ds0264eu0100 rev.1.00 page 34 of 95 feb 23, 2016 s124 2. electrical characteristics 2.2.8 iic i/o pin out put characteristics figure 2.16 v oh /v ol and i oh /i ol voltage characteristics at ta = 25c 0123456 0 10 20 30 40 50 60 70 80 90 100 110 120 i ol vs v ol v ol [v] i ol [ma] vcc = 2.7v (low drive) vcc = 3.3v (low drive) vcc = 5.5v (low drive) vcc = 5.5 v (middle drive) vcc = 3.3v (middle drive) vcc = 2.7v (middle drive)
r01ds0264eu0100 rev.1.00 page 35 of 95 feb 23, 2016 s124 2. electrical characteristics 2.2.9 operating and standby current table 2.11 operating and standby current (1) (1/2) conditions: vcc = avcc0 = 1.6 to 5.5 v item symbol typ* 9 max unit test conditions supply current* 1 high-speed mode* 2 normal mode all peripheral clock disabled, code executing from flash* 5 iclk = 32 mhz i cc 3.6 - ma * 7 iclk = 16 mhz 2.4 - iclk = 8 mhz 1.7 - all peripheral clock disabled, coremark code executing from flash* 5 iclk = 32 mhz 5.6 - iclk = 16 mhz 3.5 - iclk = 8 mhz 2.4 - all peripheral clock enabled, code executing from flash* 5 iclk = 32 mhz 9.5 - * 8 iclk = 16 mhz 5.4 - iclk = 8 mhz 3.3 - all peripheral clock enabled, code executing from flash* 5 iclk = 32 mhz - 21.0 sleep mode all peripheral clock disabled* 5 iclk = 32 mhz 1.5 - * 7 iclk = 16 mhz 1.1 - iclk = 8 mhz 0.9 - all peripheral clock enabled* 5 iclk = 32 mhz 7.2 - * 8 iclk = 16 mhz 4.0 - iclk = 8 mhz 2.4 - increase during bgo operation* 6 2.5 - - middle-speed mode* 2 normal mode all peripheral clock disabled, code executing from flash* 5 iclk = 12 mhz i cc 1.7 - ma * 7 iclk = 8 mhz 1.5 - all peripheral clock disabled, coremark code executing from flash* 5 iclk = 12 mhz 2.7 - iclk = 8 mhz 1.9 - all peripheral clock enabled, code executing from flash* 5 iclk = 12 mhz 3.9 - * 8 iclk = 8 mhz 3.0 - all peripheral clock enabled, code executing from flash* 5 iclk = 12 mhz - 8.0 sleep mode all peripheral clock disabled* 5 iclk = 12 mhz 0.8 - * 7 iclk = 8 mhz 0.8 - all peripheral clock enabled* 5 iclk = 12 mhz 2.9 - * 8 iclk = 8 mhz 2.2 - increase during bgo operation* 6 2.5 - - low-speed mode* 3 normal mode all peripheral clock disabled, code executing from flash* 5 iclk = 1 mhz i cc 0.2 - ma * 7 all peripheral clock disabled, coremark code executing from flash* 5 iclk = 1 mhz 0.3 - all peripheral clock enabled, code executing from flash* 5 iclk = 1 mhz 0.4 - * 8 all peripheral clock enabled, code executing from flash* 5 iclk = 1 mhz - 2.0 sleep mode all peripheral clock disabled* 5 iclk = 1 mhz 0.2 - * 7 all peripheral clock enabled* 5 iclk = 1 mhz 0.3 - * 8
r01ds0264eu0100 rev.1.00 page 36 of 95 feb 23, 2016 s124 2. electrical characteristics note 1. supply current values do not include output ch arge/discharge current from all pins. the values apply when internal pull-up moss are in the off state. note 2. the clock source is hoco. note 3. the clock source is moco. note 4. the clock source is the sub-clock oscillator. note 5. this does not include bgo operation. note 6. this is the increase for programming or erasure of the rom or flash memory for data storage during program execution. note 7. pclkb and pclkd are set to divided by 64. note 8. pclkb and pclkd are the same frequency as that of iclk. note 9. vcc = 3.3 v. note 1. supply current values do not include output ch arge/discharge current from all pins. the values apply when internal pull-up mos transistors are in the off state. note 2. the iwdt and lvd are not operating. supply current* 1 low-voltage mode* 3 normal mode all peripheral clock disabled, code executing from flash* 5 iclk = 4 mhz i cc 1.4 - ma * 7 all peripheral clock disabled, coremark code executing from flash* 5 iclk = 4 mhz 1.4 - all peripheral clock enabled, code executing from flash* 5 iclk = 4 mhz 2.1 - * 8 all peripheral clock enabled, code executing from flash* 5 iclk = 4 mhz - 4.0 sleep mode all peripheral clock disabled* 5 iclk = 4 mhz 0.9 - * 7 all peripheral clock enabled* 5 iclk = 4 mhz 1.6 - * 8 subosc- speed mode* 4 normal mode all peripheral clock disabled, code executing from flash* 5 iclk = 32.768 khz i cc 5.9 - a* 7 all peripheral clock enabled, code executing from flash* 5 iclk = 32.768 khz 13.0 - * 8 all peripheral clock enabled, code executing from flash* 5 iclk = 32.768 khz - 55.0 sleep mode all peripheral clock disabled* 5 iclk = 32.768 khz 3.2 - * 7 all peripheral clock enabled* 5 iclk = 32.768 khz 10.0 - * 8 table 2.12 operating and standby current (2) conditions: vcc = avcc0 = 1.6 to 5.5 v item symbol typ* 3 max unit test conditions supply current* 1 software standby mode* 2 t a = 25c i cc 0.4 1.5 a- t a = 55c 0.6 5.5 t a = 85c 1.2 10.0 t a = 105c 2.6 40.0 increment for rtc operation with low-speed on-chip oscillator* 4 0.4 - - increment for rtc operation with sub-clock oscillator* 4 0.5 - somcr.sodrv[1:0] are 11b (low power mode 3) 1.3 - somcr.sodrv[1:0] are 00b (normal mode) table 2.11 operating and standby current (1) (2/2) conditions: vcc = avcc0 = 1.6 to 5.5 v item symbol typ* 9 max unit test conditions
r01ds0264eu0100 rev.1.00 page 37 of 95 feb 23, 2016 s124 2. electrical characteristics note 3. vcc = 3.3 v. note 4. includes the current of low-speed on -chip oscillator or sub-oscillation circuit. note 1. the reference power supply current is included in the power supply current value for d/a conversion. note 2. current is consumed only by the usbfs. note 3. includes the current supplied from the pull-up resistor of the usb_dp pin to the pull-down resistor of the host device, in addition to the current cons umed by the mcu in the suspended state. note 4. when vcc = vcc_usb = 3.3 v. table 2.13 operating and standby current (3) conditions: vcc = avcc0 = 1.6 to 5.5 v item symbol min typ max unit test conditions analog power supply current during a/d conversion (at high-speed conversion) i avcc -- 3.0ma- during a/d conversion (at low-power conversion) - - 1.0 ma - during d/a conversion* 1 -0.4 0.8ma- waiting for a/d and d/a conversion (all units) - - 1.0 a- reference power supply current during a/d conversion (at high-speed conversion) i refh0 - - 150 a- waiting for a/d conversion (all units) - - 60 na - temperature sensor i tns -75 - a- low-power analog comparator (acmplp) operating current window mode i cmplp -15 - a- comparator high-speed mode - 10 - a- comparator low-speed mode - 2 - a- usb operating current during usb communication under the following settings and conditions: ? function controller is in full-speed mode and - bulk out transfer is (64 bytes) 1 - bulk in transfer is (64 bytes) 1 ? host device is connect ed by a 1-meter usb cable from the usb port. i usbf * 2 - 3.6 (vcc) 1.1 (vcc_usb)* 4 -ma- during suspended state under the following setting and conditions: ? function controller is in full-speed mode (the usb_dp pin is pulled up) ? software standby mode ? host device is connect ed by a 1-meter usb cable from the usb port. i susp * 3 - 0.35 (vcc) 170 (vcc_usb)* 4 - a-
r01ds0264eu0100 rev.1.00 page 38 of 95 feb 23, 2016 s124 2. electrical characteristics 2.2.10 vcc rise and fall gr adient and ripple frequency note 1. when ofs1.lvdas = 0. note 2. turn the power supply voltage on according to the no rmal startup rising gradient beca use the register settings set by ofs1 are not read in boot mode. figure 2.17 ripple waveform table 2.14 rise and fall gradient characteristics conditions: vcc = avcc0 = 0 to 5.5 v item symbol min typ max unit test conditions power-on vcc rising gradient voltage monitor 0 reset disabled at startup srvcc 0.02 - 2ms/v- voltage monitor 0 reset enabled at startup* 1, * 2 0.02 - - table 2.15 rising and falling gradient and ripple frequency characteristics conditions: vcc = avcc0 = 1.6 to 5.5 v the ripple voltage must meet t he allowable ripple frequency f r(vcc) within the range between the vcc upper limit (5.5 v) and lower limit (1.6 v). when the vcc change exceeds vcc 10%, the allowable voltage change rising and falling gradient dt/dvcc must be met. item symbol min typ max unit test conditions allowable ripple frequency f r (vcc) -- 10 khz figure 2.17 v r (vcc) vcc 0.2 -- 1 mhz figure 2.17 v r (vcc) vcc 0.08 -- 10 mhz figure 2.17 v r (vcc) vcc 0.06 allowable voltage change rising and falling gradient dt/dvcc 1.0 - - ms/v when vcc change exceeds vcc 10% v r(vcc) vcc 1/f r(vcc)
r01ds0264eu0100 rev.1.00 page 39 of 95 feb 23, 2016 s124 2. electrical characteristics 2.3 ac characteristics 2.3.1 frequency note 1. the lower-limit frequency of iclk is 1 mhz while pr ogramming or erasing the flash memory. when using iclk for programming or erasing the flash memo ry at below 4 mhz, the frequency can be set to 1 mhz, 2 mhz, or 3 mhz. a non-integer frequency such as 1.5 mhz cannot be set. note 2. the frequency accuracy of iclk must be 3.5% while programming or erasing the flash memory. confirm the frequency accuracy of the clock source. note 3. the lower-limit frequency of pclkd is 4 mhz at 2.4 v or above and 1 mhz at below 2.4 v when the 14-bit a/d converter is in use. note 4. see section 8, clock generation circuit in user?s manual for the relationship of frequencies between iclk, pclkb, and pclkd. note 1. the lower-limit frequency of iclk is 1 mhz while pr ogramming or erasing the flash memory. when using iclk for programming or erasing the flash memory at below 4 mhz , the frequency can be set to 1 mhz, 2 mhz, or 3 mhz. a non-integer frequency such as 1.5 mhz cannot be set. note 2. the frequency accuracy of iclk must be 3.5% while programming or erasing the flash memory. confirm the frequency accuracy of the clock source. note 3. the lower-limit frequency of pclkd is 4 mhz at 2.4 v or above and 1 mhz at below 2.4 v when the 14-bit a/d converter is in use. note 4. see section 8, clock generation circuit in user?s manual for the relationship of frequencies between iclk, pclkb, and pclkd. table 2.16 operation frequency in high-speed operating mode conditions: vcc = avcc0 = 2.4 to 5.5 v item symbol min typ max unit operation frequency system clock (iclk)* 1, * 2, * 4 2.7 to 5.5 v f 0.032768 - 32 mhz 2.4 to 2.7 v 0.032768 - 16 peripheral module clock (pclkb)* 4 2.7 to 5.5 v - - 32 2.4 to 2.7 v - - 16 peripheral module clock (pclkd)* 3, * 4 2.7 to 5.5 v - - 64 2.4 to 2.7 v - - 16 table 2.17 operation frequency in middle-speed mode conditions: vcc = avcc0 = 1.8 to 5.5 v item symbol min typ max unit operation frequency system clock (iclk)* 1, * 2, * 4 2.7 to 5.5 v f 0.032768 - 12 mhz 2.4 to 2.7 v 0.032768 - 12 1.8 to 2.4 v 0.032768 - 8 peripheral module clock (pclkb)* 4 2.7 to 5.5 v - - 12 2.4 to 2.7 v - - 12 1.8 to 2.4 v - - 8 peripheral module clock (pclkd)* 3, * 4 2.7 to 5.5 v - - 12 2.4 to 2.7 v - - 12 1.8 to 2.4 v - - 8
r01ds0264eu0100 rev.1.00 page 40 of 95 feb 23, 2016 s124 2. electrical characteristics note 1. the lower-limit frequency of iclk is 1 mh z while programming or erasing the flash memory. note 2. the frequency accuracy of iclk must be 3.5% while programming or erasing the flash memory. confirm the frequency accuracy of the clock source. note 3. the lower-limit frequency of pclkd is 1 mhz when the a/d converter is in use. note 4. see section 8, clock generation circuit in user?s manual for the relationship of frequencies between iclk, pclkb, and pclkd. note 1. the lower-limit frequency of iclk is 1 mhz while pr ogramming or erasing the flash memory. when using iclk for programming or erasing the flash memory at below 4 mhz, the frequency can be set to 1 mhz, 2 mhz, or 3 mhz. a non-integer frequency such as 1.5 mhz cannot be set. note 2. the frequency accuracy of iclk must be 3.5% while programming or erasing the flash memory. confirm the frequency accuracy of the clock source. note 3. the lower-limit frequency of pclkd is 4 mhz at 2.4 v or above and 1 mhz at below 2.4 v when the 14-bit a/d converter is in use. note 4. see section 8, clock generation circuit in user?s manual for the relationship of frequencies between iclk, pclkb, and pclkd. note 1. programming and erasing the flash memory is not possible. note 2. the 14-bit a/d converter cannot be used. note 3. see section 8, clock generation circuit in user?s manual for the relationship of frequencies between iclk, pclkb, and pclkd. table 2.18 operation frequency in low-speed mode conditions: vcc = avcc0 = 1.8 to 5.5 v item symbol min typ max unit operation frequency system clock (iclk)* 1, * 2, * 4 1.8 to 5.5 v f 0.032768 - 1 mhz peripheral module clock (pclkb)* 4 1.8 to 5.5 v - - 1 peripheral module clock (pclkd)* 3, * 4 1.8 to 5.5 v - - 1 table 2.19 operation frequency in low-voltage mode conditions: vcc = avcc0 = 1.6 to 5.5 v item symbol min typ max unit operation frequency system clock (iclk)* 1, * 2, * 4 1.6 to 5.5 v f 0.032768 - 4 mhz peripheral module clock (pclkb)* 4 1.6 to 5.5 v - - 4 peripheral module clock (pclkd)* 3, * 4 1.6 to 5.5 v - - 4 table 2.20 operation frequency in subosc-speed mode conditions: vcc = avcc0 = 1.8 to 5.5 v item symbol min typ max unit operation frequency system clock (iclk)* 1, * 3 1.8 to 5.5 v f 27.8528 32.768 37.6832 khz peripheral module clock (pclkb)* 3 1.8 to 5.5 v - - 37.6832 peripheral module clock (pclkd)* 2, * 3 1.8 to 5.5 v - - 37.6832
r01ds0264eu0100 rev.1.00 page 41 of 95 feb 23, 2016 s124 2. electrical characteristics 2.3.2 clock timing table 2.21 clock timing (1/2) item symbol min typ max unit test conditions extal external clock input cycle time t xcyc 50 - - ns figure 2.18 extal external clock input high pulse width t xh 20 - - ns extal external clock input low pulse width t xl 20 - - ns extal external clock rising time t xr --5ns extal external clock falling time t xf --5ns extal external clock input wait time* 1 t exwt 0.3 - - s- extal external clock input frequency f extal --20mhz2.4 vcc 5.5 --8 1.8 vcc < 2.4 --1 1.6 vcc < 1.8 main clock oscillator oscillation frequency f main 1- 20mhz 2.4 vcc 5.5 1- 8 1.8 vcc < 2.4 1- 4 1.6 vcc < 1.8 loco clock oscillation frequency f loco 27.8528 32.768 37.6832 khz - loco clock oscillation stabilization time t loco - - 100 s figure 2.19 iwdt-dedicated clock oscillation frequency f iloco 12.75 15 17.25 khz - moco clock oscillation frequency f moco 6.8 8 9.2 mhz - moco clock oscillation stabilization time t moco --1 s- hoco clock oscillation frequency f hoco24 23.64 24 24.36 mhz ta = ?40 to ?20c 1.8 vcc 5.5 22.68 24 25.32 ta = ?40 to 85c 1.6 vcc < 1.8 23.76 24 24.24 ta = ?20 to 85c 1.8 vcc 5.5 23.52 24 24.48 ta = 85 to 105c 2.4 vcc 5.5 f hoco32 31.52 32 32.48 ta = ?40 to ?20c 1.8 vcc 5.5 30.24 32 33.76 ta = ?40 to 85c 1.6 vcc < 1.8 31.68 32 32.32 ta = ?20 to 85c 1.8 vcc 5.5 31.36 32 32.64 ta = 85 to 105c 2.4 vcc 5.5 f hoco48* 3 47.28 48 48.72 ta = ?40 to ?20c 1.8 vcc 5.5 47.52 48 48.48 ta = ?20 to 85c 1.8 vcc 5.5 47.04 48 48.96 ta = ?40 to 105c 2.4 vcc 5.5 f hoco64* 4 63.04 64 64.96 ta = ?40 to ?20c 2.4 vcc 5.5 63.36 64 64.64 ta = ?20 to 85c 2.4 vcc 5.5 62.72 64 65.28 ta = 85 to 105c 2.4 vcc 5.5 hoco clock oscillation stabilization time* 5, * 6 except low- voltage mode t hoco24 t hoco32 - - 37.1 s figure 2.20 t hoco48 - - 43.3 t hoco64 - - 80.6 low-voltage mode t hoco24 t hoco32 t hoco48 t hoco64 - - 100.9 sub-clock oscillator oscillation frequency f sub - 32.768 - khz -
r01ds0264eu0100 rev.1.00 page 42 of 95 feb 23, 2016 s124 2. electrical characteristics note 1. time until the clock can be used after the main clock oscillator stop bit (mosccr.most p) is set to 0 (operating) when the external clock is stable. note 2. after changing the setting of the sosccr.sostp bit so that the sub-clock oscill ator operates, only start using the sub-clock after the sub-clock oscillation stabilization wait time that is equal to or greater than the oscillator manufacturer?s recommended value has elapsed. note 3. the 48-mhz hoco can be used within a vcc range of 1.8 v to 5.5 v. note 4. the 64-mhz hoco can be used within a vcc range of 2.4 v to 5.5 v. note 5. this is a characteristic when the hococr.hcstp bi t is cleared to 0 (oscillation) in the moco stop state. when the hococr.hcstp bit is cleared to 0 (oscillation ) during moco oscillation, this specification is shortened by 1 s. note 6. check oscsf.hocosf to confirm whether stabilization time has elapsed. figure 2.18 xtal external clock input timing figure 2.19 loco clock oscillation start timing figure 2.20 hoco clock oscillat ion start timing (s tarted by setting the hococr.hcstp bit) figure 2.21 sub-clock os cillation start timing sub-clock oscillation stabilization time* 2 t subosc -0.5-s figure 2.21 table 2.21 clock timing (2/2) item symbol min typ max unit test conditions t xh t xcyc xtal external clock input vcc 0.5 t xl t xr t xf loco clock oscillator output lococr.lcstp t loco hoco clock hococr.hcstp t hocox *1 note 1. x = 24, 32, 48, 64 sub-clock oscillator output sosccr.sostp t subosc
r01ds0264eu0100 rev.1.00 page 43 of 95 feb 23, 2016 s124 2. electrical characteristics 2.3.3 reset timing note 1. when ofs1.lvdas = 0. note 2. when ofs1.lvdas = 1. note 3. when iwdtcr.cks[3:0] = 0000b. figure 2.22 reset input timing at power-on figure 2.23 reset input timing (1) table 2.22 reset timing item symbol min typ max unit test conditions res pulse width at power-on t reswp 3- - ms figure 2.22 not at power-on t resw 30 - - s figure 2.23 wait time after res cancellation (at power-on) lvd0 enabled* 1 t reswt -0.7-ms figure 2.22 lvd0 disabled* 2 -0.3- wait time after res cancellation (during powered-on state) lvd0 enabled* 1 t reswt2 -0.5- s figure 2.23 lvd0 disabled* 2 -0.05- reset period iwdt* 3 t reswiw -1-iwdt clock cycle figure 2.24 internal reset (except iwdt) t reswir -1-iclk cycle wait time after internal reset cancellation lvd0 enabled* 1 t reswt3 -0.5- s lvd0 disabled* 2 -0.05- vcc res t reswp internal reset t reswt res internal reset t reswt2 t resw
r01ds0264eu0100 rev.1.00 page 44 of 95 feb 23, 2016 s124 2. electrical characteristics figure 2.24 reset input timing (2) independent watchdog timer reset software reset internal reset t reswt3 t reswiw, t reswir
r01ds0264eu0100 rev.1.00 page 45 of 95 feb 23, 2016 s124 2. electrical characteristics 2.3.4 wakeup time note 1. the division ratio of iclk and pclkx is 1. the recovery time is determined by the syst em clock source. note 2. the main clock oscillator wait control register (moscwtcr) is set to 05h. note 3. the main clock oscillator wait control register (moscwtcr) is set to 00h. note 4. the hoco clock wait control register (hocowtcr) is set to 05h. note 5. the hoco clock wait control register (hocowtcr) is set to 06h. note 1. the division ratio of iclk and pclkx is 1. the recovery time is determined by the syst em clock source. note 2. the main clock oscillator wait control register (moscwtcr) is set to 05h. note 3. the main clock oscillator wait control register (moscwtcr) is set to 00h. note 4. the system clock is 12 mhz. table 2.23 timing of recovery from low power modes (1) item symbol min typ max unit test conditions recovery time from software standby mode *1 high-speed mode crystal resonator connected to main clock oscillator system clock source is main clock oscillator (20 mhz) *2 t sbymc -2 3ms figure 2.25 external clock input to main clock oscillator system clock source is main clock oscillator (20 mhz) *3 t sbyex -14 25 s system clock source is hoco *4 (hoco clock is 32 mhz) t sbyho - 43 52 s system clock source is hoco *4 (hoco clock is 48 mhz) t sbyho - 44 52 s system clock source is hoco *5 (hoco clock is 64 mhz) t sbyho - 82 110 s system clock source is moco t sbymo - 16 25 s table 2.24 timing of recovery from low power modes (2) item symbol min typ max unit test conditions recovery time from software standby mode * 1 middle-speed mode crystal resonator connected to main clock oscillator system clock source is main clock oscillator (12 mhz) * 2 t sbymc - 23 ms figure 2.25 external clock input to main clock oscillator system clock source is main clock oscillator (12 mhz) * 3 t sbyex - 2.9 10 s system clock source is hoco* 4 t sbyho - 38 50 s system clock source is moco (8 mhz) t sbymo - 3.5 5.5 s
r01ds0264eu0100 rev.1.00 page 46 of 95 feb 23, 2016 s124 2. electrical characteristics note 1. the division ratio of iclk and pclkx is 1. the recovery time is determined by the syst em clock source. note 2. the main clock oscillator wait control register (moscwtcr) is set to 05h. note 3. the main clock oscillator wait control register (moscwtcr) is set to 00h. note 1. the division ratio of iclk and pclkx is 1. the recovery time is determined by the syst em clock source. note 2. the main clock oscillator wait control register (moscwtcr) is set to 05h. note 3. the main clock oscillator wait control register (moscwtcr) is set to 00h. note 1. the sub-clock oscillator or loco itself continues oscillating in software standby mode during subosc-speed mode. table 2.25 timing of recovery from low power modes (3) item symbol min typ max unit test conditions recovery time from software standby mode * 1 low-speed mode crystal resonator connected to main clock oscillator system clock source is main clock oscillator (1 mhz) * 2 t sbymc - 23ms figure 2.25 external clock input to main clock oscillator system clock source is main clock oscillator (1 mhz) * 3 t sbyex - 28 50 s system clock source is moco (1 mhz) t sbymo - 25 35 s table 2.26 timing of recovery from low power modes (4) item symbol min typ max unit test conditions recovery time from software standby mode * 1 low-voltage mode crystal resonator connected to main clock oscillator system clock source is main clock oscillator (4 mhz)* 2 t sbymc - 23ms figure 2.25 external clock input to main clock oscillator system clock source is main clock oscillator (4 mhz)* 3 t sbyex - 108 130 s system clock source is hoco (4 mhz) t sbyho - 108 130 s table 2.27 timing of recovery from low power modes (5) item symbol min typ max unit test conditions recovery time from software standby mode* 1 subosc-speed mode system clock source is sub-clock oscillator (32.768 khz) t sbysc -0.851ms figure 2.25 system clock source is loco (32.768 khz) t sbylo - 0.85 1.2 ms
r01ds0264eu0100 rev.1.00 page 47 of 95 feb 23, 2016 s124 2. electrical characteristics figure 2.25 software standby mode cancellation timing table 2.28 timing of recovery from low power modes (6) item symbol min typ max unit test conditions recovery time from software standby mode to snooze high-speed mode system clock source is hoco t snz -3645 s- middle-speed mode system clock source is moco (8 mhz) t snz -1.33.6 s low-speed mode system clock source is moco (1 mhz) t snz -1013 s low-voltage mode system clock source is hoco (4 mhz) t snz -87110 s oscillator iclk irq software standby mode t sbysc , t sbylo oscillator iclk irq software standby mode t sbymc, t sbyex, t sbymo , t sbyho
r01ds0264eu0100 rev.1.00 page 48 of 95 feb 23, 2016 s124 2. electrical characteristics 2.3.5 nmi and irq noise filter note: 200 ns minimum in software standby mode. note 1. t pcyc indicates the pclkb cycle. note 2. t nmick indicates the cycle of the nmi digital filter sampling clock. note 3. t irqck indicates the cycle of the irqi digita l filter sampling clock (i = 0 to 7). figure 2.26 nmi interrupt input timing figure 2.27 irq interrupt input timing table 2.29 nmi and irq noise filter item symbol min typ max unit test conditions nmi pulse width t nmiw 200 -- ns nmi digital filter disabled t pcyc 2 200 ns t pcyc 2 * 1 -- t pcyc 2 > 200 ns 200 -- nmi digital filter enabled t nmick 3 200 ns t nmick 3.5 * 2 -- t nmick 3 > 200 ns irq pulse width t irqw 200 -- ns irq digital filter disabled t pcyc 2 200 ns t pcyc 2 * 1 -- t pcyc 2 > 200 ns 200 -- irq digital filter enabled t irqck 3 200 ns t irqck 3.5 * 3 -- t irqck 3 > 200 ns t nmiw nmi t irqw irq
r01ds0264eu0100 rev.1.00 page 49 of 95 feb 23, 2016 s124 2. electrical characteristics 2.3.6 i/o ports, poeg , gpt, agt, kint, and adc14 trigger timing note 1. constraints on agtio input: t pcyc 2 (t pcyc : pclkb cycle) < t acyc. figure 2.28 i/o ports input timing figure 2.29 poeg in put trigger timing figure 2.30 gpt input capture timing table 2.30 i/o ports, po eg, gpt, agt, kint, and adc14 trigger timing item symbol min max unit test conditions i/o ports input data pulse width t prw 1.5 - t pcyc figure 2.28 poeg poeg input trigger pulse width t poew 3 - t pcyc figure 2.29 gpt input capture pulse width single edge t gticw 1.5 - t pdcyc figure 2.30 dual edge 2.5 - agt agtio, agtee input cycle 2.7 v vcc 5.5 v t acyc * 1 250 - ns figure 2.31 2.4 v vcc < 2.7 v 500 - ns 1.8 v vcc < 2.4 v 1000 - ns 1.6 v vcc < 1.8 v 2000 - ns agtio, agtee input high level width, low-level width 2.7 v vcc 5.5 v t ackwh , t ackwl 100 - ns 2.4 v vcc < 2.7 v 200 - ns 1.8 v vcc < 2.4 v 400 - ns 1.6 v vcc < 1.8 v 800 - ns agtio, agto, agtoa, agtob output frequency 2.7 v vcc 5.5 v t acyc2 62.5 - ns figure 2.31 2.4 v vcc < 2.7 v 125 - ns 1.8 v vcc < 2.4 v 250 - ns 1.6 v vcc < 1.8 v 500 - ns adc14 14-bit a/d converter trigger input pulse width t trgw 1.5 - t pcyc figure 2.32 kint key interrupt input low-level width t kr 250 - ns figure 2.33 port t prw poeg input trigger t poew input capture t gticw
r01ds0264eu0100 rev.1.00 page 50 of 95 feb 23, 2016 s124 2. electrical characteristics figure 2.31 agt i/o timing figure 2.32 adc14 trigger input timing figure 2.33 key inte rrupt input timing 2.3.7 cac timing note 1. t pbcyc : pclkb cycle. note 2. t cac : cac count clock source cycle. table 2.31 cac timing item symbol min typ max unit test conditions cac cacref input pulse width t pbcyc tcac* 2 t cacref 4.5 t cac + 3 t pbcyc -- ns - t pbcyc > tcac* 2 5 t cac + 6.5 t pbcyc -- ns t acyc2 agtio, agtee (input) t acyc t ackwl t ackwh agtio, agto, agtoa, agtob (output) adtrg0 t trgw kr00 to kr07 t kr
r01ds0264eu0100 rev.1.00 page 51 of 95 feb 23, 2016 s124 2. electrical characteristics 2.3.8 sci timing note 1. t pcyc : pclkb cycle. table 2.32 sci timing (1) conditions: vcc = avcc0 = 1.6 to 5.5 v item symbol min max unit *1 test conditions sci input clock cycle asynchronous t scyc 4 - t pcyc figure 2.34 clock synchronous 6 - input clock pulse width t sckw 0.4 0.6 t scyc input clock rise time t sckr -20ns input clock fall time t sckf -20ns output clock cycle asynchronous t scyc 6 - t pcyc clock synchronous 4 - output clock pulse width t sckw 0.4 0.6 t scyc output clock rise time 1.8v or above t sckr -20ns 1.6v or above - 30 output clock fall time 1.8v or above t sckf -20ns 1.6v or above - 30 transmit data delay (master) clock synchro nous 1.8v or above t txd -40ns figure 2.35 1.6v or above - 45 transmit data delay (slave) clock synchro nous 2.7v or above - 55 ns 2.4v or above - 60 1.8v or above - 100 1.6v or above - 125 receive data setup time (master) clock synchro nous 2.7v or above t rxs 45 - ns 2.4v or above 55 - 1.8v or above 90 - 1.6v or above 110 - receive data setup time (slave) clock synchro nous 2.7v or above 40 - ns 1.6v or above 45 - receive data hold time (master) clock synchronous t rxh 5 - ns receive data hold time (slave) clock synchronous t rxh 40 - ns
r01ds0264eu0100 rev.1.00 page 52 of 95 feb 23, 2016 s124 2. electrical characteristics figure 2.34 sck clock input timing figure 2.35 sci input/output timing in clock synchronous mode t sckw t sckr t sckf t scyc sckn (n = 0, 1, 9) t txd t rxs t rxh txdn rxdn sckn n = 0, 1, 9
r01ds0264eu0100 rev.1.00 page 53 of 95 feb 23, 2016 s124 2. electrical characteristics note 1. t pcyc : pclkb cycle table 2.33 sci timing (2) conditions: vcc = avcc0 = 1.6 to 5.5 v item symbol min max unit* 1 test conditions simple spi sck clock cycle output (master) t spcyc 4 65536 t pcyc figure 2.36 sck clock cycle input (slave) 6 65536 sck clock high pulse width t spckwh 0.4 0.6 t spcyc sck clock low pulse width t spckwl 0.4 0.6 t spcyc sck clock rise and fall time 1.8v or above t spckr, t spckf -20ns 1.6v or above -30 data input setup time master 2.7v or above t su 45 - ns figure 2.37 to figure 2.40 2.4v or above 55 - 1.8v or above 80 - 1.6v or above 110 - slave 2.7v or above 40 - 1.6v or above 45 - data input hold time master t h 33.3 - ns slave 40 - ss input setup time t lead 1- t spcyc ss input hold time t lag 1- t spcyc data output delay master 1.8v or above t od -40ns 1.6v or above - 50 slave 2.4v or above - 65 1.8v or above - 100 1.6v or above - 125 data output hold time master 2.7v or above t oh ?10 - ns 2.4v or above ?20 - 1.8v or above ?30 - 1.6v or above ?40 - slave ?10 - data rise and fall time master t dr, t df -20ns slave 1.8v or above - 20 1.6v or above - 30 simple spi slave access time t sa -6 t pcyc figure 2.40 slave output release time t rel -6 t pcyc
r01ds0264eu0100 rev.1.00 page 54 of 95 feb 23, 2016 s124 2. electrical characteristics figure 2.36 sci simple spi mode clock timing figure 2.37 sci simple spi mo de timing (master, ckph = 1) t spckwh v oh v oh v ol v ol v oh v oh t spckwl t spckr t spckf v ol t spcyc t spckwh v ih v ih v il v il v ih v ih t spckwl t spckr t spckf v il t spcyc v oh = 0.7 vcc, v ol = 0.3 vcc, v ih = 0.7 vcc, v il = 0.3 vcc (n = 0, 1, 9) sckn master select output sckn slave select input t dr, t df t su t h t oh t od msb in data lsb in msb in msb out data lsb out idle msb out sckn ckpol = 0 output sckn ckpol = 1 output mison input mosin output (n = 0, 1, 9)
r01ds0264eu0100 rev.1.00 page 55 of 95 feb 23, 2016 s124 2. electrical characteristics figure 2.38 sci simple spi mo de timing (master, ckph = 0) figure 2.39 sci simple spi mode timing (slave, ckph = 1) t su t h t oh t od msb in data lsb in msb in msb out data lsb out idle msb out sckn ckpol = 1 output sckn ckpol = 0 output mison input mosin output (n = 0, 1, 9) t dr, t df t dr, t df t su t h t lead t td t lag t sa msb in data lsb in msb in msb out data lsb out msb in msb out t oh t od t rel ssn input sckn ckpol = 0 input sckn ckpol = 1 input mison output mosin input (n = 0, 1, 9)
r01ds0264eu0100 rev.1.00 page 56 of 95 feb 23, 2016 s124 2. electrical characteristics figure 2.40 sci simple spi mode timing (slave, ckph = 0) note: t iiccyc : iic internal reference clock (iic ) cycle. note 1. cb indicates the total capacity of the bus line. table 2.34 sci timing (3) conditions: vcc = avcc0 = 2.7 to 5.5 v item symbol min max unit test conditions simple iic (standard mode) sda input rise time t sr - 1000 ns figure 2.41 sda input fall time t sf - 300 ns sda input spike pulse removal time t sp 04 t iiccyc ns data input setup time t sdas 250 - ns data input hold time t sdah 0 - ns scl, sda capacitive load c b * 1 - 400 pf simple iic (fast mode) scl, sda input rise time t sr - 300 ns figure 2.41 scl, sda input fall time t sf - 300 ns scl, sda input spike pulse removal time t sp 04 t iiccyc ns data input setup time t sdas 100 - ns data input hold time t sdah 0 - ns scl, sda capacitive load c b * 1 - 400 pf t dr, t df t sa t oh t lead t td t lag t h lsb out (last data) data msb out msb in data lsb in msb in lsb out t su t od t rel msb out ssn input sckn ckpol = 1 input sckn ckpol = 0 input mison output mosin input (n = 0, 1, 9)
r01ds0264eu0100 rev.1.00 page 57 of 95 feb 23, 2016 s124 2. electrical characteristics figure 2.41 sci simple iic mode timing sdan scln v ih v il t stah t sclh t scll p* 1 s* 1 t sf t sr t scl t sdah t sdas t stas t sp t stos p* 1 t buf sr* 1 note 1. s, p, and sr indicate the following conditions: s: start condition p: stop condition sr: restart condition (n = 0, 1, 9)
r01ds0264eu0100 rev.1.00 page 58 of 95 feb 23, 2016 s124 2. electrical characteristics 2.3.9 spi timing table 2.35 spi timing (1/2) conditions: middle drive output is selected in the drive strength control bit in the pmnpfs register . item symbol min max unit *1 test conditions spi rspck clock cycle master t spcyc 2 4096 t pcyc figure 2.42 c = 30 p f slave 6 4096 rspck clock high pulse width master t spckwh (t spcyc ? t spckr ? t spckf ) / 2 ? 3 - ns slave 3 t pcyc - rspck clock low pulse width master t spckwl (t spcyc ? t spckr ? t spckf ) / 2 ? 3 - ns slave 3 t pcyc - rspck clock rise and fall time output 2.7v or above t spckr, t spckf -10ns 2.4v or above - 15 1.8v or above - 20 1.6v or above - 30 input - 1 s data input setup time master t su 10 - ns figure 2.43 to figure 2.48 c = 30 p f slave 2.4v or above 10 - 1.8v or above 15 - 1.6v or above 20 - data input hold time master (rspck is pclkb/2) t hf 0 - ns master (rspck is not pclkb/2) t h t pcyc - slave t h 20 - ssl setup time master t lead ? 30 + n x t spcyc * 2 -ns slave 6 x t pcyc -ns ssl hold time master t lag ? 30 + n x t spcyc * 3 -ns slave 6 x t pcyc -ns
r01ds0264eu0100 rev.1.00 page 59 of 95 feb 23, 2016 s124 2. electrical characteristics note 1. t pcyc : pclkb cycle. note 2. n is set as an integer from 1 to 8 by the spckd register. note 3. n is set as an integer from 1 to 8 by the sslnd register. spi data output delay master 2.7v or above t od - 14 ns figure 2.43 to figure 2.48 c = 30 p f 2.4v or above - 20 1.8v or above - 25 1.6v or above - 30 slave 2.7v or above - 50 2.4v or above - 60 1.8v or above - 85 1.6v or above - 110 data output hold time master t oh 0- ns slave 0 - successive transmission delay master t td t spcyc + 2 t pcyc 8 t spcyc + 2 t pcyc ns slave 6 t pcyc - mosi and miso rise and fall time output 2.7v or above t dr, t df - 10 ns 2.4v or above - 15 1.8v or above - 20 1.6v or above - 30 input - 1s ssl rise and fall time output 2.7v or above t sslr, t sslf - 10 ns 2.4v or above - 15 1.8v or above - 20 1.6v or above - 30 input - 1 s slave access time 2.7v or above t sa - 2 t pcyc +50 ns figure 2.47 and figure 2.48 c = 30 p f 2.4v or above - 2 t pcyc +60 1.8v or above - 2 t pcyc +85 1.6v or above - 2 t pcyc +110 slave output release time 2.7v or above t rel - 2 t pcyc +50 ns 2.4v or above - 2 t pcyc +60 1.8v or above - 2 t pcyc +85 1.6v or above - 2 t pcyc +110 table 2.35 spi timing (2/2) conditions: middle drive output is selected in the drive strength control bit in the pmnpfs register . item symbol min max unit *1 test conditions
r01ds0264eu0100 rev.1.00 page 60 of 95 feb 23, 2016 s124 2. electrical characteristics figure 2.42 spi clock timing figure 2.43 spi timing (master , cpha = 0) (bit rate: pclkb division ratio is set to any value other than 1/2) rspcka master select output rspcka slave select input t spckwh v oh v oh v ol v ol v oh v oh t spckwl t spckr t spckf v ol t spcyc t spckwh v ih v ih v il v il v ih v ih t spckwl t spckr t spckf v il t spcyc v oh = 0.7 vcc, v ol = 0.3 vcc, v ih = 0.7 vcc, v il = 0.3 vcc t dr, t df t su t h t lead t td t lag t sslr, t sslf t oh t od msb in data lsb in msb in msb out data lsb out idle msb out ssla0 to ssla3 output rspcka cpol = 0 output rspcka cpol = 1 output misoa input mosia output
r01ds0264eu0100 rev.1.00 page 61 of 95 feb 23, 2016 s124 2. electrical characteristics figure 2.44 spi timing (master, cpha = 0) (bit rate: pclkb di vision ratio is set to 1/2) figure 2.45 spi timing (master , cpha = 1) (bit rate: pclkb division ratio is set to any value other than 1/2) ssla0 to ssla3 output rspcka cpol = 0 output rspcka cpol = 1 output misoa input mosia output lsb in t dr, t df t su t hf t lead t td t lag t sslr, t sslf t oh t od msb in msb out data lsb out idle msb out msb in data t hf t su t h t lead t td t lag t sslr, t sslf t oh t od msb in data lsb in msb in msb out data lsb out idle msb out ssla0 to ssla3 output rspcka cpol = 0 output rspcka cpol = 1 output misoa input mosia output t dr, t df
r01ds0264eu0100 rev.1.00 page 62 of 95 feb 23, 2016 s124 2. electrical characteristics figure 2.46 spi timing (master, cpha = 1) (bit rate: pclkb di vision ratio is set to 1/2) figure 2.47 spi timing (slave, cpha = 0) t su t hf t lead t td t lag t sslr, t sslf t oh t od msb in data lsb in msb in msb out data lsb out idle msb out ssla0 to ssla3 output rspcka cpol = 0 output rspcka cpol = 1 output misoa input mosia output t dr, t df t h t dr, t df t su t h t lead t td t lag t sa msb in data lsb in msb in msb out data lsb out msb in msb out t oh t od t rel ssla0 input rspcka cpol = 0 input rspcka cpol = 1 input misoa output mosia input
r01ds0264eu0100 rev.1.00 page 63 of 95 feb 23, 2016 s124 2. electrical characteristics figure 2.48 spi timing (slave, cpha = 1) ssla0 input rspcka cpol = 0 input rspcka cpol = 1 input misoa output mosia input t dr, t df t sa t oh t lead t td t lag t h lsb out (last data) data msb out msb in data lsb in msb in lsb out t su t od t rel msb out
r01ds0264eu0100 rev.1.00 page 64 of 95 feb 23, 2016 s124 2. electrical characteristics 2.3.10 iic timing note: t iiccyc : iic internal reference clock (iic ) cycle, t pcyc : pclkb cycle note 1. values in parentheses apply when icmr3.nf[1:0] is se t to 11b while the digital filter is enabled with icfer.nfe table 2.36 iic timing conditions: vcc = avcc0 = 2.7 to 5.5 v item symbol min* 1 , * 2 max unit test conditions iic (standard mode, smbus) scl input cycle time t scl 6 (12) t iiccyc + 1300 - ns figure 2.49 scl input high pulse width t sclh 3 (6) t iiccyc + 300 - ns scl input low pulse width t scll 3 (6) t iiccyc + 300 - ns scl, sda input rise time t sr - 1000 ns scl, sda input fall time t sf - 300 ns scl, sda input spike pulse removal time t sp 0 1 (4) t iiccyc ns sda input bus free time (when wakeup function is disabled) t buf 3 (6) t iiccyc + 300 - ns sda input bus free time (when wakeup function is enabled) t buf 3 (6) t iiccyc + 4 t pcyc + 300 - ns start condition input hold time (when wakeup function is disabled) t stah t iiccyc + 300 - ns start condition input hold time (when wakeup function is enabled) t stah 1 (5) t iiccyc + t pcyc + 300 - ns repeated start condition input setup time t stas 1000 - ns stop condition input setup time t stos 1000 - ns data input setup time t sdas t iiccyc + 50 - ns data input hold time t sdah 0 - ns scl, sda capacitive load c b - 400 pf iic (fast mode) scl input cycle time t scl 6 (12) t iiccyc + 600 - ns figure 2.49 scl input high pulse width t sclh 3 (6) t iiccyc + 300 - ns scl input low pulse width t scll 3 (6) t iiccyc + 300 - ns scl, sda input rise time t sr 20 (external pullup voltage/5.5v)* 2 300 ns scl, sda input fall time t sf 20 (external pullup voltage/5.5v)* 2 300 ns scl, sda input spike pulse removal time t sp 0 1 (4) t iiccyc ns sda input bus free time (when wakeup function is disabled) t buf 3 (6) t iiccyc + 300 - ns sda input bus free time (when wakeup function is enabled) t buf 3 (6) t iiccyc + 4 t pcyc + 300 - ns start condition input hold time (when wakeup function is disabled) t stah t iiccyc + 300 - ns start condition input hold time (when wakeup function is enabled) t stah 1(5) t iiccyc + t pcyc + 300 - ns repeated start condition input setup time t stas 300 - ns stop condition input setup time t stos 300 - ns data input setup time t sdas t iiccyc + 50 - ns data input hold time t sdah 0 - ns scl, sda capacitive load c b - 400 pf
r01ds0264eu0100 rev.1.00 page 65 of 95 feb 23, 2016 s124 2. electrical characteristics set to 1. note 2. only supported for scl0_a and sda0_a. figure 2.49 i 2 c bus interface input/output timing sda0 and sda1 scl0 and scl1 v ih v il t stah t sclh t scll p* 1 s* 1 t sf t sr t scl t sdah t sdas t stas t sp t stos p* 1 t buf sr* 1 note 1. s, p, and sr indica te the following conditions. s: start condition p: stop condition sr: restart condition
r01ds0264eu0100 rev.1.00 page 66 of 95 feb 23, 2016 s124 2. electrical characteristics 2.3.11 clkout timing note 1. when the extal external clock input or an oscillator is used wi th division by 1 (the ckocr. ckosel[2:0] bits are 011b and the ckocr.ckodiv[2:0] bits are 000b) to output from clkout, the above should be satisfied with an input duty cycle of 45 to 55%. note 2. when the moco is selected as the clock output source (t he ckocr.ckosel[2:0] bits are 001b) , set the clock output divisio n ratio selection to be divided by 2 (the ckocr.ckodiv[2:0] bits are 001b). figure 2.50 clkout output timing table 2.37 clkout timing item symbol min max unit* 1 test conditions clkout clkout pin output cycle* 1 vcc = 2.7 v or above t ccyc 62.5 - ns figure 2.50 vcc = 1.8 v or above 125 - vcc = 1.6 v or above 250 - clkout pin high pulse width* 2 vcc = 2.7 v or above t ch 15 - ns vcc = 1.8 v or above 30 - vcc = 1.6 v or above 150 - clkout pin low pulse width* 2 vcc = 2.7 v or above t cl 15 - ns vcc = 1.8 v or above 30 - vcc = 1.6 v or above 150 - clkout pin output rise time vcc = 2.7 v or above t cr -12ns vcc = 1.8 v or above - 25 vcc = 1.6 v or above - 50 clkout pin output fall time vcc = 2.7 v or above t cf -12ns vcc = 1.8 v or above - 25 vcc = 1.6 v or above - 50 t cf t ch t ccyc t cr t cl clkout pin output test conditions: v oh = vcc 0.7, v ol = vcc 0.3, i oh = -1.0 ma, i ol = 1.0 ma, c = 30 pf
r01ds0264eu0100 rev.1.00 page 67 of 95 feb 23, 2016 s124 2. electrical characteristics 2.4 usb characteristics 2.4.1 usbfs timing figure 2.51 usb_dp and usb_dm output timing table 2.38 usb characteristics conditions: vcc = avcc0 = vcc_usb = 3.0 to 5.5, ta = ?20 to +85c item symbol min max unit test conditions input characteristics input high level voltage v ih 2.0 - v - input low level voltage v il -0.8v- differential input sensitivity v di 0.2 - v | usb_dp ? usb_dm | differential common mode range v cm 0.8 2.5 v - output characteristics output high level voltage v oh 2.8 vcc_usb v i oh = ?200 a output low level voltage v ol 0.0 0.3 v i ol = 2 ma cross-over voltage v crs 1.3 2.0 v figure 2.51 , figure 2.52 , figure 2.53 rise time fs t r 420ns ls 75 300 fall time fs t f 420ns ls 75 300 rise/fall time ratio fs t r /t f 90 111.11 % ls 80 125 output resistance z drv 28 44 (adjusting the resistance of external elements is not necessary.) vbus characteristics vbus input voltage v ih vcc 0.8 - v - v il -vcc 0.2v- pull-up, pull-down pull-down resistor r pd 14.25 24.80 k - pull-up resistor r pui 0.9 1.575 k during idle state r pua 1.425 3.09 k during reception battery charging specification ver 1.2 d + sink current i dp_sink 25 175 a- d ? sink current i dm_sink 25 175 a- dcd source current i dp_src 713 a- data detection voltage v dat_ref 0.25 0.4 v - d + source voltage v dp_src 0.5 0.7 v output current = 250 a d ? source voltage v dm_src 0.5 0.7 v output current = 250 a usb_dp, usb_dm t f t r 90% 10% 10% 90% v crs
r01ds0264eu0100 rev.1.00 page 68 of 95 feb 23, 2016 s124 2. electrical characteristics figure 2.52 test circuit for full-speed (fs) connection figure 2.53 test circuit for low-speed (ls) connection 2.4.2 usb external supply table 2.39 usb regulator item min typ max unit test conditions vcc_usb supply current vcc_usb_ldo 3.8v -- 50 ma - vcc_usb_ldo 4.5v -- 100 ma - vcc_usb supply voltage 3.0 - 3.6 v - observation point 50 pf usb_dp usb_dm 50 pf observation point 200 pf to 600 pf usb_dp usb_dm 200 pf to 600 pf 1.5 k ? 3.6 v observation point
r01ds0264eu0100 rev.1.00 page 69 of 95 feb 23, 2016 s124 2. electrical characteristics 2.5 adc14 characteristics figure 2.54 avcc0 to vrefh0 voltage range table 2.40 a/d conversion characteristics (1) in high-speed mode (1/2) conditions: vcc = avcc0 = 4.5 to 5.5 v, vrefh0 = 4.5 to 5.5 v, vss = avss0 = vrefl0 = 0v reference voltage range applied to the vrefh0 and vrefl0. item min typ max unit test conditions frequency 1 - 64 mhz - analog input capacitance cs - - 15 pf high-precision channel - - 30 pf normal-precision channel analog input resistance rs - - 2.5 k ? - analog input voltage range ain 0 - vrefh0 v - 12-bit mode resolution - - 12 bit - conversion time* 1 (operation at pclkd = 64 mhz) permissible signal source impedance max. = 0.3 k ? 0.70 - - s high-precision channel adcsr.adhsc = 0 adsstrn.sst[7:0] = 0dh 1.13 - - s normal-precision channel adcsr.adhsc = 0 adsstrn.sst[7:0] = 28h offset error - 0.5 4.5 lsb high-precision channel 6.0 lsb other than above full-scale error - 0.75 4.5 lsb high-precision channel 6.0 lsb other than above quantization error - 0.5 - lsb - absolute accuracy - 1.25 5.0 lsb high-precision channel 8.0 lsb other than above dnl differential nonlinearity error - 1.0 - lsb - inl integral nonlinearity error - 1.0 3.0 lsb - 14-bit mode resolution - - 14 bit - conversion time* 1 (operation at pclkd = 64 mhz) permissible signal source impedance max. = 0.3 k ? 0.80 - - s high-precision channel adcsr.adhsc = 0 adsstrn.sst[7:0] = 0dh 1.22 - - s normal-precision channel adcsr.adhsc = 0 adsstrn.sst[7:0] = 28h vrefh0 5.0 4.0 3.0 2.0 1.0 1.0 2.0 3.0 4.0 5.0 a/d conversion characteristics (2) adcsr.adhsc = 0 5.5 2.7 2.4 2.4 2.7 5.5 avcc0 vrefh0 5.0 4.0 3.0 2.0 1.0 1.0 2.0 3.0 4.0 5.0 adcsr.adhsc = 1 5.5 2.7 2.4 2.4 2.7 5.5 avcc0 1.8 1.8 a/d conversion characteristics (1) a/d conversion characteristics (3) a/d conversion characteristics (4) a/d conversion characteristics (5) a/d conversion characteristics (6)
r01ds0264eu0100 rev.1.00 page 70 of 95 feb 23, 2016 s124 2. electrical characteristics note: the characteristics apply when no pin functions other than 14-bit a/d converter input are used. absolute accuracy does not include quantization errors. offset erro r, full-scale error, dnl differential nonlinearity error, and inl integral nonlinearity error do not include quantization errors. note 1. the conversion time is the sum of the sampling time and the comparison time. the number of sampling states is indicated for the test conditions. offset error - 2.0 18 lsb high-precision channel 24.0 lsb other than above full-scale error - 3.0 18 lsb high-precision channel 24.0 lsb other than above quantization error - 0.5 - lsb - absolute accuracy - 5.0 20 lsb high-precision channel 32.0 lsb other than above dnl differential nonlinearity error - 4.0 - lsb - inl integral nonlinearity error - 4.0 12.0 lsb - table 2.41 a/d conversion characteristics (2) in high-speed mode (1/2) conditions: vcc = avcc0 = 2.7 to 5.5 v, vrefh0 = 2.7 to 5.5 v, vss = avss0 = vrefl0 = 0v reference voltage range applied to the vrefh0 and vrefl0. item min typ max unit test conditions frequency 1 - 48 mhz - analog input capacitance cs - - 15 pf high-precision channel - - 30 pf normal-precision channel analog input resistance rs - - 2.5 k ? - analog input voltage range ain 0 - vrefh0 v - 12-bit mode resolution - - 12 bit - conversion time* 1 (operation at pclkd = 48 mhz) permissible signal source impedance max. = 0.3 k ? 0.94 - - s high-precision channel adcsr.adhsc = 0 adsstrn.sst[7:0] = 0dh 1.50 - - s normal-precision channel adcsr.adhsc = 0 adsstrn.sst[7:0] = 28h offset error - 0.5 4.5 lsb high-precision channel 6.0 lsb other than above full-scale error - 0.75 4.5 lsb high-precision channel 6.0 lsb other than above quantization error - 0.5 - lsb - absolute accuracy - 1.25 5.0 lsb high-precision channel 8.0 lsb other than above dnl differential nonlinearity error - 1.0 - lsb - inl integral nonlinearity error - 1.0 3.0 lsb - 14-bit mode resolution - - 14 bit - conversion time* 1 (operation at pclkd = 48 mhz) permissible signal source impedance max. = 0.3 k ? 1.06 - - s high-precision channel adcsr.adhsc = 0 adsstrn.sst[7:0] = 0dh 1.63 - - s normal-precision channel adcsr.adhsc = 0 adsstrn.sst[7:0] = 28h table 2.40 a/d conversion characteristics (1) in high-speed mode (2/2) conditions: vcc = avcc0 = 4.5 to 5.5 v, vrefh0 = 4.5 to 5.5 v, vss = avss0 = vrefl0 = 0v reference voltage range applied to the vrefh0 and vrefl0. item min typ max unit test conditions
r01ds0264eu0100 rev.1.00 page 71 of 95 feb 23, 2016 s124 2. electrical characteristics note: the characteristics apply when no pin functions other than 14-bit a/d converter input are used. absolute accuracy does not include quantization errors. offset erro r, full-scale error, dnl differential nonlinearity error, and inl integral nonlinearity error do not include quantization errors. note 1. the conversion time is the sum of the sampling time and the comparison time. the number of sampling states is indicated for the test conditions. offset error - 2.0 18 lsb high-precision channel 24.0 lsb other than above full-scale error - 3.0 18 lsb high-precision channel 24.0 lsb other than above quantization error - 0.5 - lsb - absolute accuracy - 5.0 20 lsb high-precision channel 32.0 lsb other than above dnl differential nonlinearity error - 4.0 - lsb - inl integral nonlinearity error - 4.0 12.0 lsb - table 2.42 a/d conversion characteristics (3) in high-speed mode (1/2) conditions: vcc = avcc0 = 2.4 to 5.5 v, vrefh0 = 2.4 to 5.5 v, vss = avss0 = vrefl0 = 0v reference voltage range applied to the vrefh0 and vrefl0. item min typ max unit test conditions frequency 1 - 32 mhz - analog input capacitance cs - - 15 pf high-precision channel - - 30 pf normal-precision channel analog input resistance rs - - 2.5 k ? - analog input voltage range ain 0 - vrefh0 v - 12-bit mode resolution - - 12 bit - conversion time* 1 (operation at pclkd = 32 mhz) permissible signal source impedance max. = 1.3 k ? 1.41 - - s high-precision channel adcsr.adhsc = 0 adsstrn.sst[7:0] = 0dh 2.25 - - s normal-precision channel adcsr.adhsc = 0 adsstrn.sst[7:0] = 28h offset error - 0.5 4.5 lsb high-precision channel 6.0 lsb other than above full-scale error - 0.75 4.5 lsb high-precision channel 6.0 lsb other than above quantization error - 0.5 - lsb - absolute accuracy - 1.25 5.0 lsb high-precision channel 8.0 lsb other than above dnl differential nonlinearity error - 1.0 - lsb - inl integral nonlinearity error - 1.0 3.0 lsb - 14-bit mode resolution - - 14 bit - conversion time* 1 (operation at pclkd = 32 mhz) permissible signal source impedance max. = 1.3 k ? 1.59 - - s high-precision channel adcsr.adhsc = 0 adsstrn.sst[7:0] = 0dh 2.44 - - s normal-precision channel adcsr.adhsc = 0 adsstrn.sst[7:0] = 28h table 2.41 a/d conversion characteristics (2) in high-speed mode (2/2) conditions: vcc = avcc0 = 2.7 to 5.5 v, vrefh0 = 2.7 to 5.5 v, vss = avss0 = vrefl0 = 0v reference voltage range applied to the vrefh0 and vrefl0. item min typ max unit test conditions
r01ds0264eu0100 rev.1.00 page 72 of 95 feb 23, 2016 s124 2. electrical characteristics note: the characteristics apply when no pin functions other than 14-bit a/d converter input are used. absolute accuracy does not include quantization errors. offset erro r, full-scale error, dnl differential nonlinearity error, and inl integral nonlinearity error do not include quantization errors. note 1. the conversion time is the sum of the sampling time and the comparison time. the number of sampling states is indicated for the test conditions. offset error - 2.0 18 lsb high-precision channel 24.0 lsb other than above full-scale error - 3.0 18 lsb high-precision channel 24.0 lsb other than above quantization error - 0.5 - lsb - absolute accuracy - 5.0 20 lsb high-precision channel 32.0 lsb other than above dnl differential nonlinearity error - 4.0 - lsb - inl integral nonlinearity error - 4.0 12.0 lsb - table 2.43 a/d conversion characteristics (4) in low power mode (1/2) conditions: vcc = avcc0 = 2.7 to 5.5 v, vrefh0 = 2.7 to 5.5 v, vss = avss0 = vrefl0 = 0v reference voltage range applied to the vrefh0 and vrefl0. item min typ max unit test conditions frequency 1 - 24 mhz - analog input capacitance cs - - 15 pf high-precision channel - - 30 pf normal-precision channel analog input resistance rs - - 2.5 k ? - analog input voltage range ain 0 - vrefh0 v - 12-bit mode resolution - - 12 bit - conversion time* 1 (operation at pclkd = 24 mhz) permissible signal source impedance max. = 1.1 k ? 2.25 - - s high-precision channel adcsr.adhsc = 1 adsstrn.sst[7:0] = 0dh 3.38 - - s normal-precision channel adcsr.adhsc = 1 adsstrn.sst[7:0] = 28h offset error - 0.5 4.5 lsb high-precision channel 6.0 lsb other than above full-scale error - 0.75 4.5 lsb high-precision channel 6.0 lsb other than above quantization error - 0.5 - lsb - absolute accuracy - 1.25 5.0 lsb high-precision channel 8.0 lsb other than above dnl differential nonlinearity error - 1.0 - lsb - inl integral nonlinearity error - 1.0 3.0 lsb - 14-bit mode resolution - - 14 bit - conversion time* 1 (operation at pclkd = 24 mhz) permissible signal source impedance max. = 1.1 k ? 2.50 - - s high-precision channel adcsr.adhsc = 1 adsstrn.sst[7:0] = 0dh 3.63 - - s normal-precision channel adcsr.adhsc = 1 adsstrn.sst[7:0] = 28h table 2.42 a/d conversion characteristics (3) in high-speed mode (2/2) conditions: vcc = avcc0 = 2.4 to 5.5 v, vrefh0 = 2.4 to 5.5 v, vss = avss0 = vrefl0 = 0v reference voltage range applied to the vrefh0 and vrefl0. item min typ max unit test conditions
r01ds0264eu0100 rev.1.00 page 73 of 95 feb 23, 2016 s124 2. electrical characteristics note: the characteristics apply when no pin functions other than 14-bit a/d converter input are used. absolute accuracy does not include quantization errors. offset erro r, full-scale error, dnl differential nonlinearity error, and inl integral nonlinearity error do not include quantization errors. note 1. the conversion time is the sum of the sampling time and the comparison time. the number of sampling states is indicated for the test conditions. offset error - 2.0 18 lsb high-precision channel 24.0 lsb other than above full-scale error - 3.0 18 lsb high-precision channel 24.0 lsb other than above quantization error - 0.5 - lsb - absolute accuracy - 5.0 20 lsb high-precision channel 32.0 lsb other than above dnl differential nonlinearity error - 4.0 - lsb - inl integral nonlinearity error - 4.0 12.0 lsb - table 2.44 a/d conversion characteristics (5) in low power mode (1/2) conditions: vcc = avcc0 = 2.4 to 5.5 v, vrefh0 = 2.4 to 5.5 v, vss = avss0 = vrefl0 = 0v reference voltage range applied to the vrefh0 and vrefl0. item min typ max unit test conditions frequency 1 - 16 mhz - analog input capacitance cs - - 15 pf high-precision channel - - 30 pf normal-precision channel analog input resistance rs - - 2.5 k ? - analog input voltage range ain 0 - vrefh0 v - 12-bit mode resolution - - 12 bit - conversion time* 1 (operation at pclkd = 16 mhz) permissible signal source impedance max. = 2.2 k ? 3.38 - - s high-precision channel adcsr.adhsc = 1 adsstrn.sst[7:0] = 0dh 5.06 - - s normal-precision channel adcsr.adhsc = 1 adsstrn.sst[7:0] = 28h offset error - 0.5 4.5 lsb high-precision channel 6.0 lsb other than above full-scale error - 0.75 4.5 lsb high-precision channel 6.0 lsb other than above quantization error - 0.5 - lsb - absolute accuracy - 1.25 5.0 lsb high-precision channel 8.0 lsb other than above dnl differential nonlinearity error - 1.0 - lsb - inl integral nonlinearity error - 1.0 3.0 lsb - 14-bit mode resolution - - 14 bit - conversion time* 1 (operation at pclkd = 16 mhz) permissible signal source impedance max. = 2.2 k ? 3.75 - - s high-precision channel adcsr.adhsc = 1 adsstrn.sst[7:0] = 0dh 5.44 - - s normal-precision channel adcsr.adhsc = 1 adsstrn.sst[7:0] = 28h table 2.43 a/d conversion characteristics (4) in low power mode (2/2) conditions: vcc = avcc0 = 2.7 to 5.5 v, vrefh0 = 2.7 to 5.5 v, vss = avss0 = vrefl0 = 0v reference voltage range applied to the vrefh0 and vrefl0. item min typ max unit test conditions
r01ds0264eu0100 rev.1.00 page 74 of 95 feb 23, 2016 s124 2. electrical characteristics note: the characteristics apply when no pin functions other than 14-bit a/d converter input are used. absolute accuracy does not include quantization errors. offset erro r, full-scale error, dnl differential nonlinearity error, and inl integral nonlinearity error do not include quantization errors. note 1. the conversion time is the sum of the sampling time and the comparison time. the number of sampling states is indicated for the test conditions. offset error - 2.0 18 lsb high-precision channel 24.0 lsb other than above full-scale error - 3.0 18 lsb high-precision channel 24.0 lsb other than above quantization error - 0.5 - lsb - absolute accuracy - 5.0 20 lsb high-precision channel 32.0 lsb other than above dnl differential nonlinearity error - 4.0 - lsb - inl integral nonlinearity error - 4.0 12.0 lsb - table 2.45 a/d conversion characteristics (6) in low power mode (1/2) conditions: vcc = avcc0 = 1.8 to 5.5 v (avcc0 = vcc when vcc < 2.0 v), vrefh0 = 1.8 to 5.5 v, vss = avss0 = vrefl0 = 0 v reference voltage range applied to the vrefh0 and vrefl0. item min typ max unit test conditions frequency 1 - 8 mhz - analog input capacitance cs - - 15 pf high-precision channel - - 30 pf normal-precision channel analog input resistance rs - - 2.5 k ? - analog input voltage range ain 0 - vrefh0 v - 12-bit mode resolution - - 12 bit - conversion time* 1 (operation at pclkd = 8 mhz) permissible signal source impedance max. = 5 k ? 6.75 - - s high-precision channel adcsr.adhsc = 1 adsstrn.sst[7:0] = 0dh 10.13 - - s normal-precision channel adcsr.adhsc = 1 adsstrn.sst[7:0] = 28h offset error - 1.0 7.5 lsb high-precision channel 10.0 lsb other than above full-scale error - 1.5 7.5 lsb high-precision channel 10.0 lsb other than above quantization error - 0.5 - lsb - absolute accuracy - 3.0 8.0 lsb high-precision channel 12.0 lsb other than above dnl differential nonlinearity error - 1.0 - lsb - inl integral nonlinearity error - 1.0 3.0 lsb - 14-bit mode resolution - - 14 bit - conversion time* 1 (operation at pclkd = 8 mhz) permissible signal source impedance max. = 5 k ? 7.50 - - s high-precision channel adcsr.adhsc = 1 adsstrn.sst[7:0] = 0dh 10.88 - - s normal-precision channel adcsr.adhsc = 1 adsstrn.sst[7:0] = 28h table 2.44 a/d conversion characteristics (5) in low power mode (2/2) conditions: vcc = avcc0 = 2.4 to 5.5 v, vrefh0 = 2.4 to 5.5 v, vss = avss0 = vrefl0 = 0v reference voltage range applied to the vrefh0 and vrefl0. item min typ max unit test conditions
r01ds0264eu0100 rev.1.00 page 75 of 95 feb 23, 2016 s124 2. electrical characteristics note: the characteristics apply when no pin functions other than 14-bit a/d converter input are used. absolute accuracy does not include quantization errors. offset erro r, full-scale error, dnl differential nonlinearity error, and inl integral nonlinearity error do not include quantization errors. note 1. the conversion time is the sum of the sampling time and the comparison time. the number of sampling states is indicated for the test conditions. offset error - 4.0 30.0 lsb high-precision channel 40.0 lsb other than above full-scale error - 6.0 30.0 lsb high-precision channel 40.0 lsb other than above quantization error - 0.5 - lsb - absolute accuracy - 12.0 32.0 lsb high-precision channel 48.0 lsb other than above dnl differential nonlinearity error - 4.0 - lsb - inl integral nonlinearity error - 4.0 12.0 lsb - table 2.46 a/d conversion characteristics (7) in low power mode (1/2) conditions: vcc = avcc0 = 1.6 to 5.5 v (avcc0 = vcc when vcc < 2.0 v), vrefh0 = 1.6 to 5.5 v, vss = avss0 = vrefl0 = 0 reference voltage range applied to the vrefh0 and vrefl0. item min typ max unit test conditions frequency 1 - 4 mhz - analog input capacitance cs - - 15 pf high-precision channel - - 30 pf normal-precision channel analog input resistance rs - - 2.5 k ? - analog input voltage range ain 0 - vrefh0 v - 12-bit mode resolution - - 12 bit - conversion time* 1 (operation at pclkd = 4 mhz) permissible signal source impedance max. = 9.9 k ? 13.5 - - s high-precision channel adcsr.adhsc = 1 adsstrn.sst[7:0] = 0dh 20.25 - - s normal-precision channel adcsr.adhsc = 1 adsstrn.sst[7:0] = 28h offset error - 1.0 7.5 lsb high-precision channel 10.0 lsb other than above full-scale error - 1.5 7.5 lsb high-precision channel 10.0 lsb other than above quantization error - 0.5 - lsb - absolute accuracy - 3.0 8.0 lsb high-precision channel 12.0 lsb other than above dnl differential nonlinearity error - 1.0 - lsb - inl integral nonlinearity error - 1.0 3.0 lsb - 14-bit mode resolution - - 14 bit - conversion time* 1 (operation at pclkd = 4 mhz) permissible signal source impedance max. = 9.9 k ? 15.0 - - s high-precision channel adcsr.adhsc = 1 adsstrn.sst[7:0] = 0dh 21.75 - - s normal-precision channel adcsr.adhsc = 1 adsstrn.sst[7:0] = 28h table 2.45 a/d conversion characteristics (6) in low power mode (2/2) conditions: vcc = avcc0 = 1.8 to 5.5 v (avcc0 = vcc when vcc < 2.0 v), vrefh0 = 1.8 to 5.5 v, vss = avss0 = vrefl0 = 0 v reference voltage range applied to the vrefh0 and vrefl0. item min typ max unit test conditions
r01ds0264eu0100 rev.1.00 page 76 of 95 feb 23, 2016 s124 2. electrical characteristics note: the characteristics apply when no pin functions other than 14-bit a/d converter input are used. absolute accuracy does not include quantization errors. offset erro r, full-scale error, dnl differential nonlinearity error, and inl integral nonlinearity error do not include quantization errors. note 1. the conversion time is the sum of the sampling time and the comparison time. the number of sampling states is indicated for the test conditions. note 1. the internal reference voltage cannot be selected for input channels when avcc0 < 2.0 v. note 2. the 14-bit a/d internal reference voltage indicates the voltage when the internal reference voltage is input to the 14-bit a/d converter. offset error - 4.0 30.0 lsb high-precision channel 40.0 lsb other than above full-scale error - 6.0 30.0 lsb high-precision channel 40.0 lsb other than above quantization error - 0.5 - lsb - absolute accuracy - 12.0 32.0 lsb high-precision channel 48.0 lsb other than above dnl differential nonlinearity error - 4.0 - lsb - inl integral nonlinearity error - 4.0 12.0 lsb - table 2.47 14-bit a/d converter channel classification classification channel conditions remarks high-precision channel an000 to an010 avcc0 = 1.6 to 5.5 v pins an000 to an010 cannot be used as general i/o, ts transmission, when the a/d converter is in use. normal-precision channel an016 to an022 internal reference voltage input channel internal reference voltage avcc0 = 2.0 to 5.5 v - temperature sensor input channel temperature sensor output avcc0 = 2.0 to 5.5 v - table 2.48 a/d internal reference voltage characteristics conditions: vcc = avcc0 = vrefh0 = 2.0 to 5.5 v* 1 item min typ max unit test conditions internal reference voltage input channel* 2 1.36 1.43 1.50 v - table 2.46 a/d conversion characteristics (7) in low power mode (2/2) conditions: vcc = avcc0 = 1.6 to 5.5 v (avcc0 = vcc when vcc < 2.0 v), vrefh0 = 1.6 to 5.5 v, vss = avss0 = vrefl0 = 0 reference voltage range applied to the vrefh0 and vrefl0. item min typ max unit test conditions
r01ds0264eu0100 rev.1.00 page 77 of 95 feb 23, 2016 s124 2. electrical characteristics figure 2.55 illustration of 14-bit a/d converter characteristic terms absolute accuracy absolute accuracy is the difference between output code based on the theoretical a/d conversion characteristics, and the actual a/d conversion result. when measuring absolute accuracy, the voltage at the midpoint of the width of the analog input voltage (1-lsb width), which can meet the expectation of outputting an equal code based on the theoretical a/d conversion characteristics, is used as th e analog input voltage. for ex ample, if 12-bit resolution is used and the reference voltage vrefh0 = 3.072 v, then 1-lsb width becomes 0.75 mv , and 0 mv, 0.75 mv, and 1.5 mv are used as the analog input voltages. if analog inpu t voltage is 6 mv, an absolute accuracy of 5 lsb means that th e actual a/d conversion result is in the range of 003h to 00dh, though an output code of 008h can be expected from the theoretical a/d conversion characteristics. integral nonlinearity error (inl) integral nonlinearity error is the maximum deviation between the ideal line when the meas ured offset and full-scale errors are zeroed, and the actual output code. differential nonlinearity error (dnl) differential nonlinearity error is the difference between 1-lsb width base d on the ideal a/d conver sion characteristics and the width of the actual output code. offset error offset error is the difference between the transition point of the ideal first output code and the actual first output code. full-scale error full-scale error is the difference between th e transition point of the ideal last output code and the actual last output code. integral nonlinearity error (inl) actual a/d conversion characteristic ideal a/d conversion characteristic analog input voltage offset error absolute accuracy differential nonlinearity error (dnl) full-scale error fffh 000h 0 ideal line of actual a/d conversion characteristic 1-lsb width for ideal a/d conversion characteristic differential nonlinearity error (dnl) 1-lsb width for ideal a/d conversion characteristic vrefh0 (full-scale) a/d converter output code
r01ds0264eu0100 rev.1.00 page 78 of 95 feb 23, 2016 s124 2. electrical characteristics 2.6 dac12 characteristics figure 2.56 illustration of d/a converter characteristic terms integral nonlinearity error (inl) integral nonlinearity error is the maximum deviation between the ideal output voltage based on the ideal conversion characteristic when the measured of fset and full-scale errors are zer oed, and the actual output voltage. differential nonlinearity error (dnl) differential nonlinearity erro r is the difference between 1-lsb voltage width based on the ideal d/a conversion characteristics and the width of the actual output voltage. table 2.49 d/a conversion characteristics conditions: vcc = avcc0 = 1.8 to 5.5 v reference voltage = avcc0 or avss0 selected item min typ max unit test conditions resolution - - 12 bit - resistive load 30 - - k ? - capacitive load - - 50 pf - output voltage range 0.35 - avcc0 ? 0.47 v - dnl differential nonlinearity error - 0.5 2.0 lsb - inl integral nonlinearity error - 2.0 8.0 lsb - offset error - -30mv- full-scale error - -30mv- output impedance - 5- ? - conversion time - -30 s- 000h d/a converter input code fffh output analog voltage upper output limit lower output limit offset error ideal output voltage 1-lsb width for ideal d/a conversion characteristic differential nonlinearity error (dnl) actual d/a conversion characteristic *1 integral nonlinearity error (inl) full-scale error gain error offset error ideal output voltage note 1. ideal d/a conversion output voltage that is adjusted so that offset and full scale errors are zeroed.
r01ds0264eu0100 rev.1.00 page 79 of 95 feb 23, 2016 s124 2. electrical characteristics offset error offset error is the difference between the highest actual output voltage that falls below the lower output limit and the ideal output voltage based on the input code. full-scale error full-scale error is the difference between the lowest actual output voltage that exceeds the upper ou tput limit and the ideal output voltage based on the input code. 2.7 tsn characteristics 2.8 osc stop detect characteristics figure 2.57 oscillation stop detection timing table 2.50 tsn characteristics conditions: vcc = avcc0 = 2.0 to 5.5 v item symbol min typ max unit test conditions relative accuracy - - 1.5 - c 2.4 v or above - 2.0 - c below 2.4 v temperature slope -- ?3.65 - mv/c - output voltage (at 25c) -- 1.05 - v vcc = 3.3 v temperature sensor start time t start -- 5 s- sampling time - 5 - - s table 2.51 oscillation stop detection circuit characteristics item symbol min typ max unit test conditions detection time t dr --1ms figure 2.57 t dr main clock ostdsr.ostdf moco clock iclk
r01ds0264eu0100 rev.1.00 page 80 of 95 feb 23, 2016 s124 2. electrical characteristics 2.9 por and lvd characteristics note 1. these characteristics apply when noise is not super imposed on the power supply. wh en a setting causes this voltage detection level to overlap with t hat of the voltage detection circuit (lvd2), it can not be specified whether lvd1 or lvd2 is used for voltage detection. note 2. # in the symbol v det0_# denotes the value of the ofs1.vdsel1[2:0] bits. note 3. # in the symbol v det1_# denotes the value of the lvdlvlr.lvd1lvl[4:0] bits. note 4. # in the symbol v det2_# denotes the value of the lv dlvlr.lvd2lvl[2:0] bits. table 2.52 power-on reset circuit and voltag e detection circuit characteristics (1) conditions: vcc = avcc0 item symbol min typ max unit test conditions voltage detection level* 1 power-on reset (por) v por 1.27 1.42 1.57 v figure 2.58 , figure 2.59 voltage detection circuit (lvd0)* 2 v det0_0 3.68 3.85 4.00 v figure 2.60 at falling edge vcc v det0_1 2.68 2.85 2.96 v det0_2 2.38 2.53 2.64 v det0_3 1.78 1.90 2.02 v det0_4 1.60 1.69 1.82 voltage detection circuit (lvd1)* 3 v det1_0 4.13 4.29 4.45 v figure 2.61 at falling edge vcc v det1_1 3.98 4.16 4.30 v det1_2 3.86 4.03 4.18 v det1_3 3.68 3.86 4.00 v det1_4 2.98 3.10 3.22 v det1_5 2.89 3.00 3.11 v det1_6 2.79 2.90 3.01 v det1_7 2.68 2.79 2.90 v det1_8 2.58 2.68 2.78 v det1_9 2.48 2.58 2.68 v det1_a 2.38 2.48 2.58 v det1_b 2.10 2.20 2.30 v det1_c 1.84 1.96 2.05 v det1_d 1.74 1.86 1.95 v det1_e 1.63 1.75 1.84 v det1_f 1.60 1.65 1.73 voltage detection circuit (lvd2)* 4 v det2_0 4.11 4.31 4.48 v figure 2.62 at falling edge vcc v det2_1 3.97 4.17 4.34 v det2_2 3.83 4.03 4.20 v det2_3 3.64 3.84 4.01 table 2.53 power-on reset circuit and voltage detection circuit characteristics (2) (1/2) conditions: vcc = avcc0 item symbol min typ max unit test conditions wait time after voltage monitoring 0 , 1,2 reset cancellation lvd0:enable* 1 t lvd0,1,2 -0.6- s- lvd0:disable* 2 t lvd1,2 -0.2- s- response delay* 3 t det - - 350 s figure 2.58 , figure 2.59 minimum vcc down time t voff 450 - - s figure 2.58 , vcc = 1.0 v or above power-on reset enable time t w (por) 1- - ms figure 2.59 , vcc = below 1.0 v
r01ds0264eu0100 rev.1.00 page 81 of 95 feb 23, 2016 s124 2. electrical characteristics note 1. when ofs1.lvdas = 0 note 2. when ofs1.lvdas = 1 note 3. the minimum vcc down time indicates the time when vcc is below the minimum value of voltage detection levels v por , v det0 , v det1 , and v det2 for the por/lvd. figure 2.58 voltage detection reset timing figure 2.59 power-on reset timing lvd operation stabilization time (after lvd is enabled) t d (e-a) - - 300 s figure 2.61 , figure 2.62 hysteresis width (por) v porh -110-mv- hysteresis width (lvd1 and lvd2) v lvh - 70 - mv v det1_0 to v det1_4 selected. -60- v det1_5 to v det1_9 selected. -50- v det1_a to v det1_b selected. -40- v det1_c to v det1_d selected. - 60 - lvd2 selected table 2.53 power-on reset circuit and voltage detection circuit characteristics (2) (2/2) conditions: vcc = avcc0 item symbol min typ max unit test conditions internal reset signal (active-low) vcc t voff t por t det v por t det 1.0 v note: t w(por) is the time required for a power-on reset to be enabled while the external power vcc is being held below the valid voltage (1.0 v). when vcc turns on, maintain t w(por) for 1.0 ms or more. internal reset signal (active-low) vcc t por v por 1.0 v t w(por) *1 t det
r01ds0264eu0100 rev.1.00 page 82 of 95 feb 23, 2016 s124 2. electrical characteristics figure 2.60 voltage detection circuit timing (v det0 ) figure 2.61 voltage detection circuit timing (v det1 ) t voff t lvd0 t det v det0 vcc internal reset signal (active-low) t det v lvh t voff v det1 vcc t det t det t lvd1 t d(e-a) lvcmpcr.lvd1e lvd1 comparator output lvd1cr0.cmpe lvd1sr.mon internal reset signal (active-low) when lvd1cr0.rn = 0 when lvd1cr0.rn = 1 v lvh t lvd1
r01ds0264eu0100 rev.1.00 page 83 of 95 feb 23, 2016 s124 2. electrical characteristics figure 2.62 voltage detection circuit timing (v det2 ) 2.10 ctsu characteristics table 2.54 ctsu characteristics conditions: vcc = avcc0 = 1.8 to 5.5 v item symbol min typ max unit test conditions external capacitance connected to tscap pin c tscap 91011nf- ts pin capacitive load c base --50pf- permissible output high current ioh - - -24 ma when the mutual capacitance method is applied t voff v det2 vcc t det t det t lvd2 t d(e-a) lvcmpcr.lvd2e lvd2 comparator output lvd2cr0.cmpe lvd2sr.mon internal reset signal (active-low) when lvd2cr0.rn = 0 when lvd2cr0.rn = 1 v lvh t lvd2
r01ds0264eu0100 rev.1.00 page 84 of 95 feb 23, 2016 s124 2. electrical characteristics 2.11 comparator characteristics table 2.55 acmplp characteristics conditions: vcc = avcc0 = 1.8 to 5.5 v, vss = avss0 = 0 v item symbol min typ max unit test conditions reference voltage range v ref 0- vcc ?1.4 v- input voltage range v i 0 - vcc v - output delay high-speed mode t d -- 1.2 s vcc = 3.0 slew rate of input signal > 50 mv/ s low-speed mode -- 5 s window mode - - 2 s offset voltage high-speed mode - - - 50 mv - low-speed mode - - - 40 mv - window mode - - - 60 mv - internal reference voltage for window mode v rfh - 0.76 vcc - v- v rfl - 0.24 vcc - v- operation stabilization wait time t cmp 100 - - s-
r01ds0264eu0100 rev.1.00 page 85 of 95 feb 23, 2016 s124 2. electrical characteristics 2.12 flash memory characteristics 2.12.1 code flash memory characteristics note 1. the reprogram/erase cycle is th e number of erasures for each block. when the reprogram/er ase cycle is n times (n = 1,000), erasing can be performed n times for each block. for instance, when 4-byte programming is performed 256 times for different addresses in 1-kb blocks, and then the entire block is erased, the reprogram/ erase cycle is counted as one. however, programming th e same address for several times as one erasure is not enabled. (overwriting is prohibited.) note 2. characteristic when using the flash memory progra mmer and the self-programming library provided by renesas electronics. note 3. this result is obtained from reliability testing. note 1. does not include the time until each operation of the flash memory is started after instructions are executed by the software. note 2. the lower-limit frequency of iclk is 1 mhz during programming or erasing the flash memory. when using iclk at below 4 mhz, the frequency can be set to 1 mhz, 2 mh z, or 3 mhz. a non-integer frequency such as 1.5 mhz cannot be set. note 3. the frequency accuracy of iclk must be 3.5% while programming or erasing the flash memory. confirm the frequency accuracy of the clock source. table 2.56 code flash characteristics (1) item symbol min typ max unit conditions reprogramming/erasure cycle* 1 n pec 1000 -- times - data hold time after 1000 times n pec t drp 20* 2, * 3 -- year t a = +85c table 2.57 code flash characteristics (2) high-speed operating mode conditions: vcc = avcc0 = 2.7 to 5.5 v item symbol iclk = 1 mhz iclk = 32 mhz unit min typ max min typ max programming time 4-byte t p4 - 116 998 - 54 506 s erasure time 1-kb t e1k - 9.03 287 - 5.67 222 ms blank check time 4-byte t bc4 -- 56.8 -- 16.6 s 1-kb t bc1k -- 1899 -- 140 s erase suspended time t sed -- 22.5 -- 10.7 s startup area switching setting time t sas - 21.9 585 - 12.1 447 ms access window time t aws - 21.9 585 - 12.1 447 ms ocd/serial programmer id setting time t osis - 21.9 585 - 12.1 447 ms flash memory mode transition wait time 1 t dis 2 -- 2 -- s flash memory mode transition wait time 2 t ms 5 -- 5 -- s
r01ds0264eu0100 rev.1.00 page 86 of 95 feb 23, 2016 s124 2. electrical characteristics note 1. does not include the time until each operation of the flash memory is started after instructions are executed by the software. note 2. the lower-limit frequency of iclk is 1 mhz during programming or erasing the flash memory. when using iclk at below 4 mhz, the frequency can be set to 1 mhz, 2 mh z, or 3 mhz. a non-integer frequency such as 1.5 mhz cannot be set. note 3. the frequency accuracy of iclk must be 3.5% while programming or erasing the flash memory. confirm the frequency accuracy of the clock source. 2.12.2 data flash memory characteristics note 1. the reprogram/erase cycle is the number of erasure for each block. when the re program/erase cycle is n times (n = 100,000), erasing can be performed n times for eac h block. for instance, when 1-byte programming is performed 1,000 times for different addresses in 1-by te blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. however, programming the same address for several times as one erasure is not enabled. (overwriting is prohibited.) note 2. characteristics when using the flash memory program mer and the self-programming library provided by renesas electronics. note 3. these results are obt ained from reliability testing. table 2.58 code flash characteristics (3) middle-speed operating mode conditions: vcc = avcc0 = 1.8 to 5.5 v, ta = -40 to +85c item symbol iclk = 1 mhz iclk = 8 mhz unit min typ max min typ max programming time 4-byte t p4 - 157 1411 - 101 966 s erasure time 1-kb t e1k - 9.10 289 - 6.10 228 ms blank check time 2-byte t bc4 -- 87.7 -- 52.5 s 1-kb t bc1k -- 1930 -- 414 s erase suspended time t sed -- 32.7 -- 21.6 s startup area switching setting time t sas - 22.8 592 - 14.2 465 ms access window time t aws - 22.8 592 - 14.2 465 ms ocd/serial programmer id setting time t osis - 22.8 592 - 14.2 465 ms flash memory mode transition wait time 1 t dis 2 -- 2 -- s flash memory mode transition wait time 2 t ms 720 -- 720 -- ns table 2.59 data flash characteristics (1) item symbol min typ max unit conditions reprogramming/erasure cycle* 1 n dpec 100000 1000000 - times - data hold time after 10000 times of n dpec t ddrp 20* 2, * 3 -- year ta = +85c after 100000 times of n dpec 5* 2, * 3 -- year after 1000000 times of n dpec -1* 2, * 3 - year ta = +25c
r01ds0264eu0100 rev.1.00 page 87 of 95 feb 23, 2016 s124 2. electrical characteristics note 1. does not include the time until each operation of the flash memory is started after instructions are executed by the software. note 2. the lower-limit frequency of iclk is 1 mhz during programming or erasing the flash memory. when using iclk at below 4 mhz, the frequency can be set to 1 mhz, 2 mh z, or 3 mhz. a non-integer frequency such as 1.5 mhz cannot be set. note 3. the frequency accuracy of iclk must be 3.5% while programming or erasing the flash memory. confirm the frequency accuracy of the clock source. note 1. does not include the time until each operation of the flash memory is started after instructions are executed by the software. note 2. the lower-limit frequency of iclk is 1 mhz during programming or erasing the flash memory. when using iclk at below 4 mhz, the frequency can be set to 1 mhz, 2 mh z, or 3 mhz. a non-integer frequency such as 1.5 mhz cannot be set. note 3. the frequency accuracy of iclk must be 3.5% while programming or erasing the flash memory. confirm the frequency accuracy of the clock source. table 2.60 data flash characteristics (2) high-speed operating mode conditions: vcc = avcc0 = 2.7 to 5.5 v item symbol iclk = 4 mhz iclk = 32 mhz unit min typ max min typ max programming time 1-byte t dp1 - 52.4 463 - 42.1 387 s erasure time 1-kb t de1k - 8.98 286 - 6.42 237 ms blank check time 1-byte t dbc1 -- 24.3 -- 16.6 s 1-kb t dbc1k -- 1872 -- 512 s suspended time during erasing t dsed -- 13.0 -- 10.7 s data flash stop recovery time t dstop 5 - -5 - - s table 2.61 data flash characteristics (3) middle-speed operating mode conditions: vcc = avcc0 = 1.8 to 5.5 v, ta = -40 to +85c item symbol iclk = 4 mhz iclk = 32 mhz unit min typ max min typ max programming time 1-byte t dp1 - 94.7 886 - 87.0 837 s erasure time 1-kb t de1k - 9.59 299 - 7.82 266 ms blank check time 1-byte t dbc1 -- 56.2 -- 50.9 s 1-kb t dbc1k -- 2.17 -- 1.21 ms suspended time during erasing t dsed -- 23.0 -- 21.0 s data flash stop recovery time t dstop 720 - -720 - -ns
r01ds0264eu0100 rev.1.00 page 88 of 95 feb 23, 2016 s124 2. electrical characteristics 2.12.3 serial wire debug (swd) figure 2.63 swd swclk timing table 2.62 swd characteristics (1) conditions: vcc = avcc0 = 2.4 to 5.5 v item symbol min typ max unit test conditions swclk clock cycle time t swckcyc 80 - - ns figure 2.63 swclk clock high pulse width t swckh 35 - - ns swclk clock low pulse width t swckl 35 - - ns swclk clock rise time t swckr -- 5 ns swclk clock fall time t swckf -- 5 ns swdio setup time t swds 16 - - ns figure 2.64 swdio hold time t swdh 16 - - ns swdio data delay time t swdd 2 - 70 ns table 2.63 swd characteristics (2) conditions: vcc = avcc0 = 1.6 to 2.4 v item symbol min typ max unit test conditions swclk clock cycle time t swckcyc 250 - - ns figure 2.63 swclk clock high pulse width t swckh 120 - - ns swclk clock low pulse width t swckl 120 - - ns swclk clock rise time t swckr -- 5 ns swclk clock fall time t swckf -- 5 ns swdio setup time t swds 50 - - ns figure 2.64 swdio hold time t swdh 50 - - ns swdio data delay time t swdd 2 - 150 ns swclk t swckcyc t swckh t swckf t swckr t swckl
r01ds0264eu0100 rev.1.00 page 89 of 95 feb 23, 2016 s124 2. electrical characteristics figure 2.64 swd input output timing swclk swdio (input) t swds t swdh swdio (output) swdio (output) swdio (output) t swdd t swdd t swdd
r01ds0264eu0100 rev.1.00 page 90 of 95 feb 23, 2016 s124 appendix 1. package dimensions appendix 1. pa ckage dimensions information on the latest version of the package dimensions or mountings is displayed in ?packages? on the renesas electronics corporation website. figure 1.1 lqfp 64-pin mass (typ) [g] 0.3 unit: mm previous code renesas code plqp0064kb-c jeita package code p-lfqfp64-10x10-0.50 ? 2015 renesas electronics corporation. all rights reserved. d e a 2 h d h e a a 1 b p c t e x y l p l 1 9.9 9.9 11.8 11.8 0.05 0.15 0.09 0 q 0.45 min nom dimensions in millimeters reference symbol max 10.0 10.0 1.4 12.0 12.0 0.20 3.5 q 0.5 0.6 1.0 10.1 10.1 12.2 12.2 1.7 0.15 0.27 0.20 8 q 0.08 0.08 0.75 note) 1. dimensions *1 and *2 do not include mold flash. 2. dimension *3 does not include trim offset. 3. pin 1 visual index feature may vary, but must be located within the hatched area. 4. chamfers at corners are optional, size may vary. h d a 2 a 1 l p l 1 detail f a c 0.25 d 48 33 32 49 17 16 1 64 f note 4 note 3 index area * 1 h e e * 2 * 3 b p e ys s m t
r01ds0264eu0100 rev.1.00 page 91 of 95 feb 23, 2016 s124 appendix 1. package dimensions figure 1.2 lqfp 48-pin mass (typ) [g] 0.2 unit: mm previous code renesas code plqp0048kb-b jeita package code p-lfqfp48-7x7-0.50 ? 2015 renesas electronics corporation. all rights reserved. d e a 2 h d h e a a 1 b p c t e x y l p l 1 6.9 6.9 8.8 8.8 0.05 0.17 0.09 0 q 0.45 min nom dimensions in millimeters reference symbol max 7.0 7.0 1.4 9.0 9.0 0.20 3.5 q 0.5 0.6 1.0 7.1 7.1 9.2 9.2 1.7 0.15 0.27 0.20 8 q 0.08 0.08 0.75 note) 1. dimensions *1 and *2 do not include mold flash. 2. dimension *3 does not include trim offset. 3. pin 1 visual index feature may vary, but must be located within the hatched area. 4. chamfers at corners are optional, size may vary. h d a 2 a 1 l p l 1 detail f a c 0.25 h e d e 36 25 25 24 13 37 48 112 f note 4 note 3 index area * 1 * 2 * 3 b p e ys s m t
r01ds0264eu0100 rev.1.00 page 92 of 95 feb 23, 2016 s124 appendix 1. package dimensions figure 1.3 lga 36-pin jeita package code renesas code previous code mass (typ.) [g] p-wflga36-4x4-0.50 pwlg0036ka-a p36fc-50-aa4-2 0.023 item dimensions d e w e a b x y y1 zd ze 4.00 0.10 4.00 0.10 0.05 0.20 0.69 0.07 0.08 0.50 0.24 0.05 (unit:mm) 0.20 0.75 0.75 s y1 s a s y s x 32x b a b m e s wb zd ze index mark b c a s wa d e e 1 2 e f dc b a 3 4 5 6 c d detail detail e detail b 0.34 0.05 0.55 0.70 0.05 0.55 0.05 0.70 0.05 0.55 0.05 0.75 0.75 0.55 0.55 r0.17 0.05 r0.17 0.05 r0.12 0.05 r0.12 0.05 r0.275 0.05 r0.35 0.05 0.75 0.55 0.05 0.70 0.05 0.55 0.75 0.55 0.05 0.70 0.05 (land pad) (aperture of solder resist) d 2.90 2.90 2012 renesas electronics corporation. all rights reserved.
r01ds0264eu0100 rev.1.00 page 93 of 95 feb 23, 2016 s124 appendix 1. package dimensions figure 1.4 qfn 64-pin 2013 renesas electronics corporation. all rights reserved. s y e lp s x ba b m a d e 48 32 33 16 17 1 64 a s b a d e 49 detail of a part exposed die pad jeita package code renesas code previous code mass(typ.)[g] p-hwqfn64-8x8-0.40 pwqn0064la-a 0.16 16 1 17 32 49 64 index area 2 2 d a lp 0.20 6.50 0.40 8.00 8.00 6.50 referance symbol min nom max dimension in millimeters 0.23 0.30 0.50 b 0.17 x a 0.80 y 0.05 0.00 0.20 e z z c d e 1 d e 2 2 2 e 0.40 0.05 1.00 1.00 0.15 0.25 a 1 c 2 8.05 7.95 8.05 7.95 z z d e 33 48 p64k8-40-9b5-3
r01ds0264eu0100 rev.1.00 page 94 of 95 feb 23, 2016 s124 appendix 1. package dimensions figure 1.5 qfn 48-pin 2013 renesas electronics corporation. all rights reserved. s y e lp s x ba b m a d e 36 24 25 12 13 1 48 a s b a d e 37 detail of a part exposed die pad jeita package code renesas code previous code mass(typ.)[g] p-hwqfn48-7x7-0.50 pwqn0048kb-a 48pjn-a 0.13 12 1 13 24 37 48 index area 2 2 d a lp 0.20 5.50 0.40 7.00 7.00 5.50 referance symbol min nom max dimension in millimeters 0.30 0.30 0.50 b 0.18 x a 0.80 y 0.05 0.00 0.25 e z z c d e 1 d e 2 2 2 e 0.50 0.05 0.75 0.75 0.15 0.25 a 1 c 2 7.05 6.95 7.05 6.95 z z d e 25 36 p48k8-50-5b4-6
r01ds0264eu0100 rev.1.00 page 95 of 95 feb 23, 2016 s124 appendix 1. package dimensions figure 1.6 qfn 40-pin s y e lp s x ba b m a d e 30 20 21 10 11 1 40 a s b a d e 31 detail of a part exposed die pad jeita package code renesas code previous code mass(typ.)[g] p-hwqfn40-6x6-0.50 pwqn0040kc-a p40k8-50-4b4-5 0.09 10 1 11 20 31 40 index area 2 2 d a lp 0.20 4.50 0.40 6.00 6.00 4.50 referance symbol min nom max dimension in millimeters 0.30 0.30 0.50 b 0.18 x a 0.80 y 0.05 0.00 0.25 e z z c d e 1 d e 2 2 2 e 0.50 0.05 0.75 0.75 0.15 0.25 a 1 c 2 6.05 5.95 6.05 5.95 z z d e 21 30
s124 datasheet revision history - 1 rev. date chapter summary 1.00 feb. 23, 2016 ? first edition issued all trademarks and registered trademarks are the property of thei r respective owners. revision history
general precautions in the handl ing of microprocessing unit and microcontroller unit products 1. precaution against electrostatic discharge (esd) a strong electrical field, when exposed to a cmos device, can cause destruction of th e gate oxide and ulti mately degrade the de vice operation. steps must be taken to stop the ge neration of static electricity as much as possible, and quickly dissipate it when it occurs. environmental control must be adequate. when it is dry, a humidifier should be used. this is recommended to avoid using insulat ors that can easily build up static electricity. semi conductor devices must be stored and transported in an anti-static container, static shielding bag or conductive mate rial. all test and meas urement tools including work benche s and floors must be grounded. the operator must also be grounded using a wrist strap. semiconductor de vices must not be touched with bare hands. similar precauti ons must be taken for printed circuit boa rds with mounted semiconductor devices. 2. processing at power-on the state of the product is undefined at the time when power is supplied. the states of internal ci rcuits in the lsi are indete rminate and the states of register settings and pins are undefined at the time when power is supplied. in a finished product where the rese t signal is applied to the external reset pin, the st ates of pins are not guaranteed from the ti me when power is supplied until the reset p rocess is completed. in a similar way, the states of pins in a product that is reset by an on-chip pow er-on reset functi on are not guaran teed from the time when power is supplied until the power reaches the le vel at which resetting is specified. 3. input of signal during power-off state do not input signals or an i/o pull-up power supply while the device is powered off. the cu rrent injection that results from in put of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. follow the guideline fo r input signal during power-off st ate as described in your produ ct documentation. 4. handling of unused pins handle unused pins in accordance with the directions given under handling of unused pins in the manual. the input pins of cmos products are generally in the high-impedance state. in operation with an unused pin in the open-circuit state, extra electromag netic noise is induced in the vicinity of the lsi, an associated shoot-through current flow s internally, and malf unctions occur due t o the false recognition of the pin state as an input si gnal become possible. 5. clock signals after applying a reset, only rele ase the reset line after the operating clock signal becomes stable. when switching the clock s ignal during program execution, wait until the targ et clock signal is stabilized. when the cl ock signal is generated with an external resonator or from an external oscillator during a rese t, ensure that the reset line is only released after full stabilization of the cloc k signal. additionally, when switching to a clock signal produced with an external resonator or by an ex ternal oscillator while program execution is in progress, wait until the target clock signal is stable. 6. voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malf unction. if the input of the cmos device stays in the area between vil (max.) and vih (min.) due to noise, for example, the device may malfunction. take care to prevent chattering noise from entering the device when the input leve l is fixed, and also in the transition pe riod when the input level passes through t he area between vil (max.) and vih (min.). 7. prohibition of access to reserved addresses access to reserved addresses is prohibited. the reserved addres ses are provided for possible future expansion of functions. do not access these addresses as the correct operation of the lsi is not guaranteed. 8. differences between products before changing from one product to another, for example to a product with a differ ent part number, confirm that the change wil l not lead to problems. the characteristics of a microprocessing unit or microcontroller un it products in the same group but having a different part number might differ in terms of internal memory capacity , layout pattern, and other factors, which can affect th e ranges of electrical characterist ics, such as characterist ic values, operating margins, immunity to noise, and amount of radiated nois e. when changing to a product with a different part number, im plement a system-evaluation test for the given product.
notice 1. descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics do es not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 3. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property right s of third parties by or arising from the use of renesas electronics products or technical information described in this document. no license, express, implied or otherwise, is granted hereby under any paten ts, copyrights or other intellectual property rights of renesas electronics or others. 4. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration, modification, copy or otherwise misappropriation of renesas electronics product. 5. renesas electronics products are classified according to the following two quality grades: "standard" and "high quality". the recommended applications for each renesas electronics product depends on the product's quality grade, as indicated below. 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